United Microelectronics Corp.

Jung-Ching Chen

Chuang-Hsin Chueh

Spring Chen

Ming-Tsung Tung

Jy-Hwang Lin

Shyan-Yhu Wang

Anchor Chen

Hwi-Huang Chen

Chih-Hung Lin

Chin-Lung Chen

Shang-Chi Wu

Sheng-Hsiung Yang

Jih-Wei Liou

Chin-Hung Liu

Chien-Ming Lin

Hsiao-Wen Liu

Chun-Ching Yu

Jim Su

Ching-Ho Yang

Yi-Hao Chen

Shu-Chun Chan

Wen-Yu Lee

A method of fabricating a high voltage device includes the step of forming a patterned photoresist layer on a conductive layer and a dielectric below the conductive. The conductive layer and the dielectric layer are patterned by taking the patterned photoresist layer as a mask. Subsequently the patterned photoresist layer is shrunk. The conductive layer and the dielectric layer are then patterned by taking the shrunk photoresist layer as a mask.

Method of fabricating high voltage device

A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region.

LDMOS with N-type isolation ring and method of fabricating the same

A method for forming a depletion-mode single-poly electrically erasable programmable read-only memory (EEPROM) cell is provided. The method includes providing a substrate having a floating region and a control region. Then, an isolation deep well and a deep well are formed in the floating region and the control region of the substrate respectively. A well region is formed in the isolation deep well simultaneously with forming an isolation well region between the isolation deep well and the deep well in the substrate. A depletion doped region and a cell implant region are formed at the well region of the substrate and the deep well of the substrate respectively. A floating gate structure is formed across over the floating region and the control region. An implantation process is performed to form a source/drain region and a heavily doped region in the depletion doped region and the cell implant region respectively.

Depletion-mode single-poly EEPROM cell

A semiconductor device is provided. An isolation structure is formed in a substrate to define a first and a second active region, and a channel active region therebetween. A field implant region is formed below a portion of the isolation structure around the first, second, and channel active regions. A channel active region includes two first sides defining a channel width. The distance from each first side to a second side of a neighboring field implant region is d. The shortest distance from a third side of each first or second active region to an extension line of each second side of the field implant region is d. R=d/d, where 0.15&#x2266;R&#x2266;0.85. A gate structure covers the channel active region and extends over a portion of the isolation structure. Source/drain doped regions are formed in the first and the second active regions.

Semiconductor device

A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.

Method for manufacturing gate oxide layer with different thicknesses

A non-volatile memory cell includes a substrate, a first isolation structure positioned in a first region on the substrate, a second isolation structure surrounding a second region on the substrate, a control gate positioned on the first isolation structure in the first region, a first insulating layer positioned on the control gate, a second insulating layer positioned on the portion of the substrate in the second region, and a floating gate positioned on the first insulating layer and the second insulating layer.

Method of manufacturing non-volatile memory cell

A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof

Electrically erasable programmable read-only memory cell and memory device

Non-volatile memory cell and manufacturing method thereof

A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.

Method for fabricating integrated circuits having both high voltage and low voltage devices

A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.

High-voltage device structure

The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a deep well encompassing the LV region and the MV region is formed in the substrate. Afterward, a plurality of n-wells and a plurality of p-wells are in the HV region, the MV region, and the LV region. Following that, a plurality of HV devices are formed in the HV region, a plurality of MV devices are formed in the MV region, and a plurality of LV devices are formed in the LV region.

Growing community of inventors

Dadu, Taiwan

Jung-Ching Chen