The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2007
Filed:
Jul. 05, 2005
Anchor Chen, Hsin-Chu, TW;
Chih-hung Lin, Hsin-Chu, TW;
Hwi-huang Chen, Hsin-Chu, TW;
Jih-wei Liou, Hsin-Chu, TW;
Chin-hung Liu, Taipei Hsien, TW;
Ming-tsung Tung, Hsin-Chu, TW;
Chien-ming Lin, Hsin-Chu, TW;
Jung-ching Chen, Tai-Chung Hsien, TW;
Anchor Chen, Hsin-Chu, TW;
Chih-Hung Lin, Hsin-Chu, TW;
Hwi-Huang Chen, Hsin-Chu, TW;
Jih-Wei Liou, Hsin-Chu, TW;
Chin-Hung Liu, Taipei Hsien, TW;
Ming-Tsung Tung, Hsin-Chu, TW;
Chien-Ming Lin, Hsin-Chu, TW;
Jung-Ching Chen, Tai-Chung Hsien, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.