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For the Inventor, By the Inventor

Morgan Hill, CA, United States of America

Juergen K Lahner

USPTO Granted Patents = 17 

Average Co-Inventor Count = 3.2

ph-index = 8

Forward Citations = 226(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (2002 - 2008)
  • Morgan Hill, CA (US) (2008 - 2011)

Company Filing History:

goldMedal10 out of 3,715 
 
Lsi Logic Corporation
 patents
silverMedal7 out of 2,353 
 
Lsi Corporation
 patents

Years Active: 2002-2011

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17 patents (USPTO):Explore Patents
1. 7895546 - Statistical design closure (2011-02-22),
2. 7844929 - Optimizing test code generation for verification environment (2010-11-30),
3. 7594201 - Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code (2009-09-22),
4. 7441210 - On-the-fly RTL instructor for advanced DFT and design closure (2008-10-21),
5. 7415687 - Method and computer program for incremental placement and routing with nested shells (2008-08-19),
6. 7412678 - Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design (2008-08-12),
7. 7380228 - Method of associating timing violations with critical structures in an integrated circuit design (2008-05-27),
8. 7086015 - Method of optimizing RTL code for multiplex structures (2006-08-01),
9. 7082584 - Automated analysis of RTL code containing ASIC vendor rules (2006-07-25),
10. 7000163 - Optimized buffering for JTAG boundary scan nets (2006-02-14),
11. 6990651 - Advanced design format library for integrated circuit design synthesis and floorplanning tools (2006-01-24),
12. 6907588 - Congestion estimation for register transfer level code (2005-06-14),
13. 6766499 - Buffer cell insertion and electronic design automation (2004-07-20),
14. 6757885 - Length matrix generator for register transfer level code (2004-06-29),
15. 6546538 - Integrated circuit having on-chip capacitors for supplying power to portions of the circuit requiring high-transient peak power (2003-04-08),

Title: Juergen K Lahner: Innovator in Statistical Design and Test Code Optimization

Introduction

Juergen K Lahner is a prominent inventor based in Morgan Hill, CA (US). He holds a total of 17 patents, showcasing his significant contributions to the fields of statistical design and test code optimization. His innovative methods have greatly impacted the efficiency and effectiveness of design closure projects.

Latest Patents

One of Lahner's latest patents is titled "Statistical Design Closure." This method involves reading statistical data from a database that defines various chip yield improvements. The process includes calculating targets for current design closure projects based on historical trends and generating resource reports for users. Another notable patent is "Optimizing Test Code Generation for Verification Environment." This method optimizes the generation of test code by reading assertions, testbenches, and target code coverage. It identifies redundant test vector sets and generates efficient test code using a subset of these vectors.

Career Highlights

Throughout his career, Juergen K Lahner has worked with notable companies such as LSI Logic Corporation and LSI Corporation. His experience in these organizations has allowed him to refine his skills and contribute to significant advancements in technology.

Collaborations

Lahner has collaborated with talented individuals, including Balamurugan Balasubramanian and Kavitha Chaturvedula. These partnerships have fostered innovation and enhanced the development of his patented methods.

Conclusion

Juergen K Lahner's work in statistical design and test code optimization has made a lasting impact on the industry. His innovative patents and collaborations reflect his dedication to advancing technology and improving design processes.

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