The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2008
Filed:
Jun. 02, 2004
Applicants:
Juergen Lahner, Sunnyvale, CA (US);
Srinivas Adusumalli, San Jose, CA (US);
Jonathan Byrn, Kasson, MN (US);
Inventors:
Juergen Lahner, Sunnyvale, CA (US);
Srinivas Adusumalli, San Jose, CA (US);
Jonathan Byrn, Kasson, MN (US);
Assignee:
LSI Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path between synchronous clock domains is defined as a false path in the integrated circuit design, then reporting a fatal violation.