The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2008
Filed:
Oct. 05, 2005
Juergen K. Lahner, Morgan Hill, CA (US);
Balamurugan Balasubramanian, Santa Clara, CA (US);
Randall P. Fry, Greenville, NC (US);
Juergen K. Lahner, Morgan Hill, CA (US);
Balamurugan Balasubramanian, Santa Clara, CA (US);
Randall P. Fry, Greenville, NC (US);
LSI Corporation, Milpitas, CA (US);
Abstract
A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and routing of the integrated circuit design is analyzed to find a critical location and is partitioned into a series of nested shells. Each shell surrounds the critical location and each preceding shell. An ordering of the shells and at least one of a timing constraint and an area constraint are selected for each shell. Each shell is placed and routed in the order selected according to the timing constraint and area constraint.