Lsi Logic Corporation

Lsi Corporation

Juergen K Lahner

Balamurugan Balasubramanian

Kavitha Chaturvedula

Srinivas Adusumalli

Stefan Graef

Benjamin Mbouombouo

Randall P Fry

Kiran Atmakuri

Juergen Dirks

Gregory Pierce

Jonathan W Byrn

Weidan Li

Human Boluki

Ludger F Johanterwage

Gopinath Kudva

Kiran Atkmakuri

Krishna Devineni

Shalini Rubdi

A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.

Statistical design closure

A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.

Optimizing test code generation for verification environment

A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and receiving as input criteria defining a critical multiplex structure. The first register transfer level code is analyzed to identify multiplex structures in the first register transfer level code. Each of the multiplex structures identified in the first register transfer level code is compared to the criteria defining a critical multiplex structure. Each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure is entered in a list of critical multiplex structures. The list of critical multiplex structures is generated as output.

Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code

A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in the file while the designer is editing the code to generate a plurality of characterization results and (C) generating a plurality of suggestions to the designer to modify the code based on a comparison of a plurality of goals for the circuit design and the characterization results.

On-the-fly RTL instructor for advanced DFT and design closure

A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and routing of the integrated circuit design is analyzed to find a critical location and is partitioned into a series of nested shells. Each shell surrounds the critical location and each preceding shell. An ordering of the shells and at least one of a timing constraint and an area constraint are selected for each shell. Each shell is placed and routed in the order selected according to the timing constraint and area constraint.

Method and computer program for incremental placement and routing with nested shells

A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path between synchronous clock domains is defined as a false path in the integrated circuit design, then reporting a fatal violation.

Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design

A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.

Method of associating timing violations with critical structures in an integrated circuit design

A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.

Method of optimizing RTL code for multiplex structures

A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.

Automated analysis of RTL code containing ASIC vendor rules

An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.

Optimized buffering for JTAG boundary scan nets

An integrated circuit design library includes a timing parameter representative of a design element in an integrated circuit; an area size parameter representative of the design element in an integrated circuit; and a routing demand parameter representative of a number of connections required for the design element for each value of the timing parameter and the area size parameter.

Advanced design format library for integrated circuit design synthesis and floorplanning tools

A method of estimating congestion for register transfer level code includes steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor plan, computing routing demand numbers for the regions in the floor plan, computing routing resource numbers for the regions in the floor plan, and generating a congestion estimate of the register transfer level code as a function of the routing demand numbers and the routing resource numbers.

Congestion estimation for register transfer level code

A computer readable medium encoded with instructions for executing the steps of: receiving information about a driving cell from a layout tool, receiving information about an interconnect from a layout tool, determining buffer cell information based upon information about the driving cell and the interconnect by accessing a previously defined library lookup table, relaying the buffer cell information from the library look up table to the layout tool.

Buffer cell insertion and electronic design automation

A method of generating a length matrix for register transfer level code includes steps for receiving as input register transfer level code, an I/O block list, a plurality of compile units, and a user defined hierarchical depth; mapping the register transfer level code to a design library, generating a connectivity matrix for the plurality of compile units, generating a priority list of interconnections from the connectivity matrix, generating placement coordinates for the compile units from the priority list of interconnections and the connectivity matrix, and generating as output at least one of the connectivity matrix and the placement coordinates.

Length matrix generator for register transfer level code

Provided is an integrated circuit (IC) device that includes a semiconductor substrate on which electronic components are formed and multiple metal layers on which wires are routed. Formed on the multiple metal layers is a capacitor that includes a first plate formed on a first metal layer and a second plate formed on a second metal layer that is adjacent to the first metal layer. An area in which the first plate and the second plate overlap has a width of at least twice the width of a typical wire on the IC device. Also provided is a technique for supplying power and ground to locations on an integrated circuit (IC) device that has multiple metal layers for routing wires and a substrate for forming electronic components. Initially, the technique identifies an overlap area where two of the multiple metal layers that are adjacent to each other have open space. A plate is then formed in the overlap area of each of the two metal layers so as to construct a capacitor. Then, one plate of the capacitor is connected to power, the other plate of the capacitor is connected to ground, and the plates of the capacitor are also connected to locations on the substrate of the IC device.

Growing community of inventors

Morgan Hill, CA, United States of America

Juergen K Lahner