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For the Inventor, By the Inventor

Wurih, Taiwan

Jr Jung Lin

USPTO Granted Patents = 14

Average Co-Inventor Count = 5.4

ph-index = 4

Forward Citations = 52(Granted Patents)


Location History:

  • Taichung, TW (2010 - 2012)
  • Wurih Township, TW (2012)
  • Wurih Township, Taichung County, TW (2010 - 2014)
  • Zhubei, TW (2014)
  • Hsinchu, TW (2016)

Company Filing History:

goldMedal14 out of 40,850 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2010-2016

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14 patents (USPTO):Explore Patents
1. 9257426 - Integrated high-k/metal gate in CMOS process flow (2016-02-09),
2. 8912610 - Structure and method for MOSFETS with high-K and metal gate structure (2014-12-16),
3. 8911559 - Method to pre-heat and stabilize etching chamber condition and improve mean time between cleaning (2014-12-16),
4. 8841731 - Integrated high-k/metal gate in CMOS process flow (2014-09-23),
5. 8791001 - N2 based plasma treatment and ash for HK metal gate protection (2014-07-29),
6. 8551837 - Methods of fabricating high-K metal gate devices (2013-10-08),
7. 8383502 - Integrated high-K/metal gate in CMOS process flow (2013-02-26),
8. 8304349 - Method to integrate gate etching as all-in-one process for high K metal gate (2012-11-06),
9. 8258588 - Sealing layer of a field effect transistor (2012-09-04),
10. 8163625 - Method for fabricating an isolation structure (2012-04-24),
11. 8148249 - Methods of fabricating high-k metal gate devices (2012-04-03),
12. 8003507 - Method of integrating high-K/metal gate in CMOS process flow (2011-08-23),
13. 7833853 - Method of defining gate structure height for semiconductor devices (2010-11-16),
14. 7776755 - Solution for polymer and capping layer removing with wet dipping in HK metal gate etching process (2010-08-17),

Title: Jr Jung Lin: Innovator in Semiconductor Technology

Introduction

Jr Jung Lin is a prominent inventor based in Wurih, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 14 patents. His work focuses on improving semiconductor devices and processes, showcasing his expertise and innovative spirit.

Latest Patents

Among his latest patents is the "Integrated high-k/metal gate in CMOS process flow." This patent describes a semiconductor device that includes a semiconductor substrate with both first-type and second-type active regions. It features a dielectric layer over the substrate, a first metal layer with a specific work function, and additional metal layers designed to enhance the device's performance. Another notable patent is the "Method to pre-heat and stabilize etching chamber condition and improve mean time between cleaning." This method outlines a process for cleaning an etching chamber, which involves introducing an inert gas and transporting a wafer into the chamber for etching.

Career Highlights

Jr Jung Lin is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His work at this company has allowed him to develop and refine his innovative ideas, contributing to advancements in semiconductor manufacturing.

Collaborations

Throughout his career, Jr Jung Lin has collaborated with talented individuals such as Ryan Chia-Jen Chen and Yih-Ann Lin. These collaborations have fostered a creative environment that encourages the exchange of ideas and the development of groundbreaking technologies.

Conclusion

Jr Jung Lin is a distinguished inventor whose work in semiconductor technology has led to numerous patents and innovations. His contributions continue to shape the future of the industry, making him a key figure in the field.

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