The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2013
Filed:
Feb. 29, 2012
Yih-ann Lin, Jhudong Township, Hsinchu County, TW;
Ryan Chia-jen Chen, Chiayi, TW;
Chien-hao Chen, Chuangwei Township, Ilan County, TW;
Kuo-tai Huang, Hsinchu, TW;
Yi-hsing Chen, Chuanghua, TW;
Jr Jung Lin, Wurih Township, Taichung County, TW;
Yu Chao Lin, Rende Township, Tainan County, TW;
Yih-Ann Lin, Jhudong Township, Hsinchu County, TW;
Ryan Chia-Jen Chen, Chiayi, TW;
Chien-Hao Chen, Chuangwei Township, Ilan County, TW;
Kuo-Tai Huang, Hsinchu, TW;
Yi-Hsing Chen, Chuanghua, TW;
Jr Jung Lin, Wurih Township, Taichung County, TW;
Yu Chao Lin, Rende Township, Tainan County, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.