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For the Inventor, By the Inventor

Kyungki-Do, South Korea

JoonYoung Choi

This inventor holds 10 USPTO granted patents and 3 published patent applications. Top assignee: Stats Chippac Pte. Ltd.. Active years: 2012-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: JoonYoung Choi. Retrieved from https://idiyas.com/inventor/joonyoung-choi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 10 

% Patents Active = 100.0

Average Co-Inventor Count = 3.1

ph-index = 3

Forward Citations = 17(Granted Patents)


Location History:

  • Kyoung-ki-do, KR (2012 - 2015)
  • Incheon, KR (2013 - 2015)
  • Guwangju-si, KR (2015)
  • Gyeonggi-do, KR (2016 - 2017)

Company Filing History:

goldMedal10 out of 1,843 
 
Stats Chippac Pte. Ltd.
 patents

Years Active: 2012-2017

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10 patents (USPTO):Explore Patents
1. 9780063 - Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer (2017-10-03),
2. 9524958 - Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bonding (2016-12-20),
3. 9252093 - Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer (2016-02-02),
4. 9093278 - Method of manufacture of integrated circuit packaging system with plasma processing (2015-07-28),
5. 9059108 - Integrated circuit packaging system with interconnects (2015-06-16),
6. 8994048 - Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integration (2015-03-31),
7. 8835301 - Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer (2014-09-16),
8. 8642469 - Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer (2014-02-04),
9. 8546194 - Integrated circuit packaging system with interconnects and method of manufacture thereof (2013-10-01),
10. 8288203 - Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump (2012-10-16),

Title: Innovations by JoonYoung Choi in Semiconductor Technology

Introduction

JoonYoung Choi is a prominent inventor based in Kyoung-ki-do, South Korea. He has made significant contributions to the field of semiconductor technology, holding a total of 10 patents. His work focuses on improving the efficiency and reliability of semiconductor devices, which are crucial components in modern electronics.

Latest Patents

Among his latest patents, JoonYoung Choi has developed a semiconductor device and a method of forming a bump structure with an insulating buffer layer to reduce stress on semiconductor wafers. This innovation involves creating a bump structure over contact pads on a semiconductor wafer, which includes a buffer layer that mitigates thermal and mechanical stress. Another notable patent is for a method of individual die bonding followed by simultaneous multiple die thermal compression bonding. This method enhances the throughput of die bonding, allowing for more efficient processing of semiconductor die.

Career Highlights

JoonYoung Choi is currently employed at Stats Chippac Pte. Ltd., where he continues to advance semiconductor technologies. His expertise and innovative approaches have positioned him as a key figure in the industry, contributing to the development of cutting-edge semiconductor solutions.

Collaborations

Throughout his career, JoonYoung has collaborated with talented individuals such as DaeSik Choi and SungWon Cho. These collaborations have fostered a creative environment that encourages the exchange of ideas and the development of innovative technologies.

Conclusion

JoonYoung Choi's contributions to semiconductor technology through his patents and collaborations highlight his role as a leading inventor in the field. His work not only enhances the performance of semiconductor devices but also paves the way for future innovations in electronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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