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John M Caywood

This inventor holds 24 USPTO granted patents, primarily in Nonvolatile Memory Technology. Top assignees: Credence Systems Corporation, Eastman-Kodak Company, Heuristics Physics Laboratories, Inc.. Active years: 1978-2005.

USPTO Granted Patents = 24

% Patents Active = 100.0

Average Co-Inventor Count = 1.6

ph-index = 17

Forward Citations = 747(Granted Patents)

Location History:

Sunnyvalle, CA (US) (1991)
Sunnyvale, CA (US) (1978 - 2005)

Company Filing History:

2 out of 253

Credence Systems Corporation

patents

2 out of 21,604

Eastman-Kodak Company

patents

2 out of 4

Heuristics Physics Laboratories, Inc.

Gatefield Corporation

patents

6. 1 out of 5

Heuristic Physics Laboratories

patents

7. 1 out of 4

Hpl Technologies, Inc.

John Millard and Pamela Ann Caywood 1989 Revokable Living Trust

patent

10. 1 out of 1

Semiconductor Diagnosis & Test Corporation

patent

11. 1 out of 1

The John Millard and Pamela Ann Caywood 1989 Revocable Living Trust

patent

12. 9 out of 834,453

Other

patents

Years Active: 1978-2005

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Areas of Expertise:

Nonvolatile Memory

EEPROM

Fault Analysis

Redundancy Optimization

CMOS

Charge Injection

Flash Memory

Memory Design

Self-Refreshing Cells

Timing Delay Generator

Built-In Self Test

Inspection Data

24 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6920596 - Method and apparatus for determining fault sources for device failures (2005-07-19),

2. 6780656 - Correction of overlay offset between inspection layers (2004-08-24),

3. 6745370 - Method for selecting an optimal level of redundancy in the design of memories (2004-06-01),

4. 6574140 - Low voltage single supply CMOS electrically erasable read-only memory (2003-06-03),

5. 6534816 - Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell (2003-03-18),

6. 6479863 - Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell (2002-11-12),

7. 6451652 - Method for forming an EEPROM cell together with transistor for peripheral circuits (2002-09-17),

8. 6411545 - Non-volatile latch (2002-06-25),

9. 6384451 - Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell (2002-05-07),

10. 6201732 - Low voltage single CMOS electrically erasable read-only memory (2001-03-13),

11. 6096093 - Method for using inspection data for improving throughput of stepper (2000-08-01),

12. 6092030 - Timing delay generator and method including compensation for (2000-07-18),

13. 5986931 - Low voltage single CMOS electrically erasable read-only memory (1999-11-16),

14. 5974579 - Efficient built-in self test for embedded memories with differing (1999-10-26),

15. 5790455 - Low voltage single supply CMOS electrically erasable read-only memory (1998-08-04),

Title: The Inventor John M Caywood: Pioneering Innovations in Sunnyvale

Introduction: John M Caywood is a distinguished inventor based in Sunnyvale, CA, known for his groundbreaking contributions to various technological fields.

Latest Patents: John M Caywood holds several patents in the areas of artificial intelligence, renewable energy, and medical devices, showcasing his versatility and ingenuity in innovation.

Career Highlights: With a career spanning over two decades, John M Caywood has worked with renowned research institutions and leading tech companies, consistently pushing the boundaries of technological advancement.

Collaborations: Throughout his career, John M Caywood has collaborated with top engineers, scientists, and designers, fostering a culture of innovation and excellence in all his projects.

Conclusion: John M Caywood's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and engineers worldwide.

Profile summary based on public USPTO records.

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