Other

Eastman-kodak Company

Credence Systems Corporation

Xicor Corporation

Heuristics Physics Laboratories, Inc.

Intel Corporation

Gatefield Corporation

Heuristic Physics Laboratories

Hpl Technologies, Inc.

The John Millard and Pamela Ann Caywood 1989 Revocable Living Trust

John Millard and Pamela Ann Caywood 1989 Revokable Living Trust

Semiconductor Diagnosis & Test Corporation

John M Caywood

Yervant D Lepejian

Julie D Segal

William H Owen

Ping Wang

Joseph Drori

James M Jaffe

Jagdish Pathak

Lawrence A Kraus

Isao Nojima

Jeffrey Sung

Timothy John Tredwell

Constantine N Anagnostopoulos

Brian Duffy

Robert J Lipp

Joseph G Nolan, Iii

Gregorio Spadea

Hovhannes Ghukasyan

Robert U Broze

Richard D Freeman

Arman Sagatelian

Hrant Marandjian

David Yepejian Lepejian

David Muradian

Alvin Jee

David Lepejian

Alan B Helffrich, Iii

A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of the fault sources from the failure signatures; generating aggregate device test data from test data of a device for the preselected tests; generating aggregate matches by comparing the aggregate failure signatures with the aggregate device test data; and determining fault sources for device failures by comparing the test data of the device with ones of the failure signatures of fault sources corresponding to the aggregate matches. An apparatus configured to perform the method comprises at least one circuit.

Method and apparatus for determining fault sources for device failures

A method for determining between at least three origins of a coordinate system used for at least three different defect inspection spaces. The method comprises: collecting multiple sets of data spanning defect inspection spaces; filtering the data sets to remove points that introduce noise into correlation calculations; determining whether different data sets show correlation; selecting pairs of data sets showing correlation greater than or equal to a metric; and calculating coordinate offsets of at least three origins based on the selected pairs of data sets.

Correction of overlay offset between inspection layers

A method for determining the number of redundancy units to employ in a memory integrated circuit. The critical areas for faults on each process layer in the integrated circuit for a range of defect sizes, and the signatures of the electrical responses of faulted circuits to input test stimuli are determined. A statistical frequency distribution for both the signatures for a ratio of defect sizes on each of the process layers, and for the occurrences of selected combinations of the signatures are determined. A ratio of the signature distribution for different numbers of redundancy units, and the die area for each of the different numbers of redundancy units are determined. The number of usable die per wafer is determined from the signature distribution and the die area. A level of redundancy that maximizes the number of usable die per wafer is selected.

Method for selecting an optimal level of redundancy in the design of memories

P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a V about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

Low voltage single supply CMOS electrically erasable read-only memory

A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent said grid insulator, a retention insulator which may employ a graded band gap disposed adjacent said grid electrode, and a floating gate disposed adjacent said retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor. In the nonvolatile memory cell, the floating gate of the tunneling charge injector is coupled to or forms a part of the floating gate of the nonvolatile memory element. The tunneling charge injector is employed to inject charge onto the floating gate of the nonvolatile memory element. A memory device includes an array of nonvolatile memory cells wherein each of the memory cells comprises a nonvolatile memory element with a floating gate such as a floating gate MOS transistor and a tunneling charge injector having a floating gate that is either coupled to the floating gate of the nonvolatile memory element or forms a portion of the floating gate of the nonvolatile memory element.

Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell

A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent the grid insulator, a retention insulator disposed adjacent the grid electrode, and a floating gate electrode disposed adjacent the retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor. In the nonvolatile memory cell, the floating gate of the tunneling charge injector is coupled to or forms a part of the floating gate of the nonvolatile memory element. The tunneling charge injector is employed to inject charge onto the floating gate of the nonvolatile memory element. A memory device includes an array of nonvolatile memory cells wherein each of the memory cells comprises a nonvolatile memory element with a floating gate such as a floating gate MOS transistor and a tunneling charge injector having a floating gate that is either coupled to the floating gate of the nonvolatile memory element or forms a portion of the floating gate of the nonvolatile memory element.

A method for forming an EEPROM cell together with transistors for peripheral circuits is disclosed. The method results in having a predetermined amount of material remaining proximate to the edge of the electrode, thereby forming a structure that extends a short distance beyond the sides of the electrode. An additional method for forming an trilayer EEPROM cell together with transistors for peripheral circuits is also disclosed, which results trilayer layer being restricted to covering the electrode and a small proximate region extending over the substrate surface. Two shoulders may also be etched into the sidewalls of the oxide layer which lie along the edges of said electrode.

Method for forming an EEPROM cell together with transistor for peripheral circuits

A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is coupled to the first complementary output node and a drain of the second MOS transistor is coupled to the second complementary output node. Each of the first and second MOS transistors have a gate cross coupled to the drain of the other one of the first and second MOS transistor. A source of a third MOS transistor is coupled to the first read/write bias node and a source of a fourth MOS transistor is coupled to the second read/write bias node. A drain of the third MOS transistor is coupled to the first complementary output node and a drain of the fourth MOS transistor is coupled to the second complementary output node. Each of the third and fourth MOS transistors have a gate cross coupled to the source of the other one of the third and fourth MOS transistors.

Non-volatile latch

A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent said grid insulator, a retention insulator disposed adjacent said grid electrode, and a floating gate electrode disposed adjacent said retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor. In the nonvolatile memory cell, the floating gate of the tunneling charge injector is coupled to or forms a part of the floating gate of the nonvolatile memory element. The tunneling charge injector is employed to inject charge onto the floating gate of the nonvolatile memory element. A memory device includes an array of nonvolatile memory cells wherein each of the memory cells comprises a nonvolatile memory element with a floating gate such as a floating gate MOS transistor and a tunneling charge injector having a floating gate that is either coupled to the floating gate of the nonvolatile memory element or forms a portion of the floating gate of the nonvolatile memory element.

P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a V,about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

Low voltage single CMOS electrically erasable read-only memory

A method for managing stepper operations required during the manufacturing of an integrated circuit die having at least one known defect, as determined by inspection, comprises the steps of determining, based upon an analysis of the connectivity and defect information relating to the die having at least one known defect a probability of failure to each at least one known defect and eliminating from stepper operations any die having at least one fatal defect.

Method for using inspection data for improving throughput of stepper

Apparatus for supplying a signal after a predetermined time delay comprises circuitry for generating a base delay signal that is synchronized to a stable master oscillator insensitive to changes in at least one environmental variable. A vernier signal delay circuit provides delay increments smaller than those available from the base delay signal, the delay increments being sensitive to said at least one environmental variable. Storage circuitry is provided for storing information related to the duration of the delay increments as function of at least one environmental variable for which correction is to be supplied. Sensing circuitry is provided for sensing the at least one environmental variable for which correction is to be provided to supply a sensed at least one environmental variable. Control signal generating circuitry is provided, responsive to the sensing means and cooperating with the storage means, for generating a control signal to the vernier signal delay means to select a desired delay from among the delay increments in response to the sensed at least one environmental variable.

Timing delay generator and method including compensation for

P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a V.sub.PP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

A built-in self test (BIST) circuit for an integrated circuit tests one or more embedded memories by writing data to each memory address, reading it back out, and then comparing the input and output data to see if they match. The BIST circuit includes one or more data generators for supplying a sequence of data to be written to the various addresses of each memory and one or more identical address generators, each for supplying addresses to a separate embedded memory during read and write operations. Though the memories may have differently sized address spaces, all address generators generate a similar address sequence having a range of address values as large or larger than the address space of the largest memory. During each memory write cycle, a separate filter checks the address output of each address generator to determine whether the address is within the address space of the corresponding memory. If so, the BIST circuit writes the current data output of a data generator to that address of the memory. If not, the BIST circuit ignores the current address and data outputs of the address and data generators and repeats the write operation it performed during a next preceding memory write cycle, writing the same data to the same valid memory address. The BIST circuit makes a similar address substitution during write operation. This allows the BIST circuit to use identical address generators for all memories regardless of the size of the memory being tested.

Growing community of inventors

Sunnyvale, CA, United States of America

John M Caywood