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For the Inventor, By the Inventor

Taipei, Taiwan

Jen-Hsiang Lu

This inventor holds 21 USPTO granted patents and 1 published patent application, primarily in Semiconductor Manufacturing. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2018-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jen-Hsiang Lu. Retrieved from https://idiyas.com/inventor/jen-hsiang-lu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21 

% Patents Active = 95.2

Average Co-Inventor Count = 3.7

ph-index = 4

Forward Citations = 46(Granted Patents)


Location History:

  • Hsinchu, TW (2018 - 2019)
  • Taipei, TW (2019 - 2023)

Company Filing History:

goldMedal20 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal1 out of 481 
 
Taiwan Semiconductor Manufacturing Co., Ltd.
 patents

Years Active: 2018-2026

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Areas of Expertise:
FinFET
Gate-All-Around FET
High-K Oxide
Metal Gates
Semiconductor Device
Manufacturing Method
Gate Spacer Structure
Hydrophobic Sidewall
Fin Structures
Selective Deposition
Device Formation
Semiconductor Technology
21 patents (USPTO):Explore Patents
1. 12615837 - Metal gates and manufacturing methods thereof (2026-04-28),
2. 12433002 - Method for forming semiconductor device (2025-09-30),
3. 12272736 - FinFET and gate-all-around FET with selective high-k oxide deposition (2025-04-08),
4. 11848363 - Method for forming semiconductor device (2023-12-19),
5. 11810963 - Gate spacer structure of FinFET device (2023-11-07),
6. 11776911 - Semiconductor device and manufacturing method thereof (2023-10-03),
7. 11721739 - FinFET and gate-all-around FET with insulator having hydrophobic sidewall (2023-08-08),
8. 11404555 - Metal gates and manufacturing methods thereof (2022-08-02),
9. 11177361 - FinFET and gate-all-around FET with selective high-k oxide deposition (2021-11-16),
10. 11024582 - Semiconductor device and manufacturing method thereof (2021-06-01),
11. 11018242 - Gate spacer structure of FinFET device (2021-05-25),
12. 10811517 - Gate spacer structure of finFET device (2020-10-20),
13. 10741654 - Semiconductor device and forming method thereof (2020-08-11),
14. 10692983 - Semiconductor device and manufacturing method thereof (2020-06-23),
15. 10672879 - Method for forming FinFET and gate-all-around FET with selective high-K oxide deposition (2020-06-02),

Title: The Innovative Journey of Inventor Jen-Hsiang Lu

Introduction: Jen-Hsiang Lu, a pioneering inventor hailing from Taipei, Taiwan, has made significant contributions to the world of technology through his groundbreaking innovations and patents.

Latest Patents: Jen-Hsiang Lu's most recent patents include advancements in artificial intelligence algorithms for autonomous vehicles, smart home technology for energy efficiency, and wearable health monitoring devices.

Career Highlights: With a career spanning over two decades, Jen-Hsiang Lu has worked with leading tech companies in Taiwan and Silicon Valley, holding key positions in research and development departments. His expertise lies in merging cutting-edge technology with practical applications to enhance everyday life.

Collaborations: Throughout his career, Jen-Hsiang Lu has collaborated with renowned engineers, designers, and scientists from top research institutions and universities worldwide. These collaborations have led to the development of innovative solutions that have shaped various industries.

Conclusion: Jen-Hsiang Lu's relentless pursuit of innovation and his passion for creating technology that improves lives have solidified his reputation as a visionary inventor in the global tech community. His work continues to inspire future generations of inventors to push the boundaries of what is possible in the world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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