Taiwan Semiconductor Manufacturing Comp. Ltd.

Jen-Hsiang Lu

Chung-Ting Li

Chih-Hao Chang

Shih-Hsun Chang

Tsung-Han Tsai

Bi-Fen Wu

Sheng-Yu Chang

Jyun-Yang Shen

Yu-Chang Lin

Hung-Ming Chen

Chih-Pin Tsao

Hou-Ju Li

Chun-Sheng Liang

Yi-Jen Chen

Chia-Chun Liao

A method includes forming a first gate spacer and a second gate spacer on a sidewall of a first gate structure. The first gate spacer is between the second gate spacer and the first gate structure. A first interlayer dielectric (ILD) layer is formed to surround the first gate spacer, the second gate spacer, and the first gate structure. A portion of the second gate spacer and a portion of the first ILD layer are removed simultaneously. A top surface of the second gate spacer is lower than a top surface of the first ILD layer.

Method for forming semiconductor device

A semiconductor device structure is provided. The semiconductor device structure includes first and second gate spacers formed over a semiconductor substrate, longitudinally extending along a first direction, and separated from each other by a gate electrode layer. A first insulating layer longitudinally extends along a second direction to pass through the gate electrode layer and the first and second gate spacers. A gate dielectric layer has a top surface covered by the gate electrode layer. The top width of the gate dielectric layer is less than that of the gate electrode layer. The first and second gate spacers and the first insulating layer have first, second and third hydrophobic surfaces, respectively. These hydrophobic surfaces are in direct contact with first, second and third sidewall surfaces of the gate electrode layer, respectively.

FinFET and gate-all-around FET with selective high-k oxide deposition

A method of forming a semiconductor device includes forming a gate structure on a semiconductor substrate. A gate spacer is formed adjacent to the gate structure. The gate spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer. A plasma treatment is performed to the second dielectric layer. After performing the plasma treatment, at least a portion of the second dielectric layer is removed such that a sidewall of the first dielectric layer is exposed. A dielectric cap is formed on the gate spacer.

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Gate spacer structure of FinFET device

A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

Semiconductor device and manufacturing method thereof

A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate. The semiconductor device structure also includes a gate dielectric layer formed between the gate electrode layer and the semiconductor substrate. In addition, the semiconductor device structure includes a first gate spacer having a hydrophobic surface that covers a first sidewall of the gate electrode layer. The first sidewall of the gate electrode layer extends along a first sidewall of the gate dielectric layer, so that the first sidewall of the gate dielectric layer is separated from the hydrophobic surface of the first gate spacer.

FinFET and gate-all-around FET with insulator having hydrophobic sidewall

A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.

Metal gates and manufacturing methods thereof

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed across the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below a portion of the gate structure and two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. In addition, the first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall, and the gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.

A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

Gate spacer structure of finFET device

A semiconductor device includes a semiconductor substrate, at least one gate stack, a gate spacer and a dielectric cap. The gate stack is located on the semiconductor substrate. The gate spacer is located on a sidewall of the gate stack. The gate spacer includes a first dielectric layer and a second dielectric layer with different etch properties. The dielectric cap at least caps the gate spacer. The dielectric cap and the second dielectric layer define a gap therebetween.

Semiconductor device and forming method thereof

In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

A method of forming a semiconductor device structure is provided. The method includes forming an isolation feature over a semiconductor substrate. The semiconductor substrate includes a fin structure over the isolation feature. Two opposing spacer elements are formed over the isolation feature and across the fin structure so as to define a gate opening. The gate opening exposes the fin structure and the isolation feature and inner sidewalls of the gate opening have carbon-containing hydrophobic surfaces. A gate structure is formed in the gate opening with the carbon-containing hydrophobic surfaces.

Method for forming FinFET and gate-all-around FET with selective high-K oxide deposition

A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.

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Taipei, Taiwan

Jen-Hsiang Lu