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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Jayanthi Pallinti

USPTO Granted Patents = 19

Average Co-Inventor Count = 3.4

ph-index = 5

Forward Citations = 83(Granted Patents)


Location History:

  • Gresham, OR (US) (2005)
  • Santa Clara, CA (US) (2000 - 2013)

Company Filing History:

goldMedal16 out of 3,715 
 
Lsi Logic Corporation
 patents
silverMedal3 out of 2,353 
 
Lsi Corporation
 patents

Years Active: 2000-2013

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19 patents (USPTO):
1. 8552560 - Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing (2013-10-08),
2. 8076779 - Reduction of macro level stresses in copper/low-K wafers (2011-12-13),
3. 7531442 - Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing (2009-05-12),
4. 7205673 - Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing (2007-04-17),
5. 6951808 - Metal planarization system (2005-10-04),
6. 6838379 - PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER (2005-01-04),
7. 6752916 - Electrochemical planarization end point detection (2004-06-22),
8. 6713394 - Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures (2004-03-30),
9. 6607967 - Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate (2003-08-19),
10. 6586326 - Metal planarization system (2003-07-01),
11. 6555475 - Arrangement and method for polishing a surface of a semiconductor wafer (2003-04-29),
12. 6503828 - Process for selective polishing of metal-filled trenches of integrated circuit structures (2003-01-07),
13. 6489242 - Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures (2002-12-03),
14. 6439981 - Arrangement and method for polishing a surface of a semiconductor wafer (2002-08-27),
15. 6424019 - Shallow trench isolation chemical-mechanical polishing process (2002-07-23),

Title: Jayanthi Pallinti - Innovator from Santa Clara, CA

Introduction: Jayanthi Pallinti is a pioneering inventor based in Santa Clara, CA, known for her groundbreaking contributions to the field of technology and innovation.

Latest Patents: Jayanthi Pallinti holds several patents in the areas of artificial intelligence, machine learning, and data analytics, showcasing her expertise in cutting-edge technologies.

Career Highlights: With a career spanning over two decades, Jayanthi Pallinti has worked with top tech companies, leading research institutions, and universities, driving innovation and pushing the boundaries of what is possible in the tech industry.

Collaborations: Throughout her career, Jayanthi Pallinti has collaborated with renowned experts in the field, fostering a culture of innovation and knowledge-sharing that has led to significant advancements in technology.

Conclusion: Jayanthi Pallinti's passion for innovation, coupled with her technical expertise, has solidified her reputation as a trailblazer in the tech industry, inspiring future generations of inventors and innovators.

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