The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
Nov. 18, 2005
Jayanthi Pallinti, Santa Clara, CA (US);
Dilip Vijay, Redwood City, CA (US);
Hemanshu Bhatt, Vancouver, WA (US);
Sey-shing Sun, Portland, OR (US);
Hong Ying, Cupertino, CA (US);
Chiyi Kao, San Jose, CA (US);
Jayanthi Pallinti, Santa Clara, CA (US);
Dilip Vijay, Redwood City, CA (US);
Hemanshu Bhatt, Vancouver, WA (US);
Sey-Shing Sun, Portland, OR (US);
Hong Ying, Cupertino, CA (US);
Chiyi Kao, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.