Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate

Abstract

A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform. The planarization process include: removing portions of the filler layer over the liner layer on the upper surface of the substrate until portions of the underlying liner layer on the upper surface of the substrate are exposed; treating the exposed portions of the liner layer to inhibit removal of the exposed liner layer portions; continuing to remove the remainder of the filler layer on the liner layer over the upper surface of the substrate until all of the underlying liner layer on the upper surface of the substrate is exposed; and then removing the liner layer over the upper surface of the substrate and over the filler layer in the trenches until all of the liner layer is removed from the upper surface of the substrate; whereby removal of all of the filler layer on the liner layer over the upper surface of the substrate, while inhibiting removal of the liner layer over the upper surface of the substrate until such filler layer removal on the liner layer over the upper surface of the substrate is completed, will result in formation of a planarized surface on the upper surface of the substrate, and the upper surfaces of the filler layer and the liner layer in the trenches.