Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures

Abstract

A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over such one or more dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose a portion of the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount of the one or more dielectric layers overlying such raised portions of the integrated circuit structure. The mask is then removed and the structure is subject to a chemical mechanical polishing step to planarize the upper surface of the structure. The prior removal of a portion of the overall volume of the one or more dielectric layers in the region overlying the raised portions of the integrated circuit structure before the planarization step results in a shortening of the CMP process which, in turn, results in a shortening of the time during which the structure is subject to the mechanical stresses of the CMP process. This inhibits or eliminates cracking of the low k dielectric layer adjacent the region of the low k dielectric layer over raised portions of the underlying integrated circuit structure.