The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2009
Filed:
Nov. 30, 2005
Jayanthi Pallinti, Santa Clara, CA (US);
Dilip Vijay, Redwood City, CA (US);
Hemanshu Bhatt, Vancouver, WA (US);
Sey-shing Sun, Portland, OR (US);
Hong Ying, Cupertino, CA (US);
Chiyi Kao, San Jose, CA (US);
Peter Burke, Portland, OR (US);
Ramaswamy Ranganathan, Saratoga, CA (US);
Qwai Low, Cupertino, CA (US);
Jayanthi Pallinti, Santa Clara, CA (US);
Dilip Vijay, Redwood City, CA (US);
Hemanshu Bhatt, Vancouver, WA (US);
Sey-Shing Sun, Portland, OR (US);
Hong Ying, Cupertino, CA (US);
Chiyi Kao, San Jose, CA (US);
Peter Burke, Portland, OR (US);
Ramaswamy Ranganathan, Saratoga, CA (US);
Qwai Low, Cupertino, CA (US);
LSI Corporation, Milpitas, CA (US);
Abstract
Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.