Lsi Logic Corporation

Lsi Corporation

Jayanthi Pallinti

Ronald J Nagahara

Sey-Shing Sun

Hemanshu D Bhatt

Dawn M Lee

Hong Ying

Dilip Vijay

Chiyi Kao

James J Xie

Peter Austin Burke

Samuel Vance Dunton

Shouli Steve Hsia

Ron J Nagahara

Akihisa Ueno

Yanhua Wang

Qwai Hoong Low

Byung-Sung Kwak

Ramaswamy Ranganathan

Weidan Li

Ming-Yi Lee

Yan Fang

William K Barth

Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.

Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing

A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 &#x3bc;m aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 &#x3bc;m. Another possibility is provide an extra 0.6 &#x3bc;m aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 &#x3bc;m aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0.6 &#x3bc;m and another barrier layer of 60 nm.

Reduction of macro level stresses in copper/low-K wafers

Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.

Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing

A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1&#x2013;2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.

Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing

A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material. The eroded portion of the metallic element is thereby restored. By removing precursor material from those areas in which no replacement with the desired material is wanted, the desired material is selectively deposited only in those place where the precursor material remains, and where it is desired to fill in the cavities or dishing that was created in the areas of the softer metallic elements between the harder laterally surrounding elements during a prior chemical mechanical polishing process. Thus, the microelectronic device is more fully planarized, as the dishing is filled in, and the metallic element is supplemented with an additional amount of desired material.

Metal planarization system

A process for forming copper metal interconnects and copper-filled vias in a dielectric layer on an integrated circuit structure wherein the impurity level of the copper-filled metal lines and copper-filled vias is lowered, resulting in an increase in the average grain size of the copper, a reduction of the resistivity, and more homogeneous distribution of the stresses related to the formation of the copper metal lines and copper-filled vias throughout the deposited copper. The process comprises: depositing a partial layer of copper metal in trenches and via openings previously formed in one or more dielectric layers, then annealing the deposited copper layer at an elevated temperature for a predetermined period of time; and then repeating both the deposit step and the step of annealing the deposited layer of copper one or more additional times until the desired final thickness is reached. After the deposition and annealing of the deposited copper, the annealed structure is then planarized preferably using, for example, a chemical mechanical polishing (CMP) process, and then the planarized structure is again annealed. Preferably the process further includes removing a thin portion of copper from the surface of the deposited and annealed copper layer.

PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER

A method for determining an end point of a planarization process for removing metal from a surface of a substrate submerged in an electrolytic solution or slurry. A first electrode is provided which is operable to contact the surface of the substrate, such as a working electrode of a potentiostat system. A second electrode is provided which is operable to contact the electrolytic solution, such as a reference electrode of the potentiostat system. The first electrode is contacted to the surface of the substrate and an electrochemical property is measured, such as the electrochemical potential between the first and second electrodes, where the electrochemical property is indicative of an electrochemical characteristic of the substrate-slurry system. The planarization process is preferably stopped when a substantial change in the electrochemical potential of the system is measured. By measuring the electrochemical potential between the substrate and slurry using the first and second electrodes during the planarization process, the present invention provides an accurate indication of the time at which the metal is completely removed from the surface of the substrate. Thus, implementation of the invention substantially reduces the probability of removing too much or too little material during planarization.

Electrochemical planarization end point detection

A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over such one or more dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose a portion of the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount of the one or more dielectric layers overlying such raised portions of the integrated circuit structure. The mask is then removed and the structure is subject to a chemical mechanical polishing step to planarize the upper surface of the structure. The prior removal of a portion of the overall volume of the one or more dielectric layers in the region overlying the raised portions of the integrated circuit structure before the planarization step results in a shortening of the CMP process which, in turn, results in a shortening of the time during which the structure is subject to the mechanical stresses of the CMP process. This inhibits or eliminates cracking of the low k dielectric layer adjacent the region of the low k dielectric layer over raised portions of the underlying integrated circuit structure.

Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures

A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform. The planarization process include: removing portions of the filler layer over the liner layer on the upper surface of the substrate until portions of the underlying liner layer on the upper surface of the substrate are exposed; treating the exposed portions of the liner layer to inhibit removal of the exposed liner layer portions; continuing to remove the remainder of the filler layer on the liner layer over the upper surface of the substrate until all of the underlying liner layer on the upper surface of the substrate is exposed; and then removing the liner layer over the upper surface of the substrate and over the filler layer in the trenches until all of the liner layer is removed from the upper surface of the substrate; whereby removal of all of the filler layer on the liner layer over the upper surface of the substrate, while inhibiting removal of the liner layer over the upper surface of the substrate until such filler layer removal on the liner layer over the upper surface of the substrate is completed, will result in formation of a planarized surface on the upper surface of the substrate, and the upper surfaces of the filler layer and the liner layer in the trenches.

Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate

An arrangement for polishing a semiconductor wafer is disclosed. The arrangement includes a plurality of preassembled polishing pad assemblies which can be selectively coupled to, and decoupled from, an actuating mechanism for rotating the polishing pad assemblies. An associated method of polishing a semiconductor wafer is also disclosed.

Arrangement and method for polishing a surface of a semiconductor wafer

The invention provides a process for selectively polishing a main electrically conductive layer of an integrated circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.

Process for selective polishing of metal-filled trenches of integrated circuit structures

A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material. A yet another step of the process includes polishing the integrated circuit substrate surface to remove a substantial portion of the composite layered stack and a portion of the insulating material adjacent to the composite layered stack at about a same rate. The polishing step facilitates in forming a substantially planar surface of the insulating material above the trench and reducing a likelihood of forming of a concave region near a middle region of the surface of the insulating material. The concave region recesses inwardly into the surface of the insulating material in the trench.

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Santa Clara, CA, United States of America

Jayanthi Pallinti