Cupertino, CA, United States of America

Jagdish G Belani

This inventor holds 10 USPTO granted patents. Top assignee: National Semiconductor Corporation. Active years: 1983-1998.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jagdish G Belani. Retrieved from https://idiyas.com/inventor/jagdish-g-belani

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.3

ph-index = 8

Forward Citations = 434(Granted Patents)


Company Filing History:


Years Active: 1983-1998

Loading Chart...
10 patents (USPTO):Explore Patents

Title: Innovations of Jagdish G Belani

Introduction

Jagdish G Belani is a prominent inventor based in Cupertino, CA, known for his significant contributions to semiconductor technology. With a total of 10 patents to his name, he has made remarkable advancements in the field, particularly in integrated circuit packaging.

Latest Patents

One of his latest innovations is the Thermal Ball Lead Integrated Package (Thermal BLIP). This invention features improved thermal performance compared to prior art BLIPs. The Thermal BLIP combines ball and lead technologies to enhance the interconnect density of the package while addressing the challenge of heat extraction capabilities. It is particularly well-suited for high power and pin count integrated circuit devices. In this design, a heat sink is attached to the top surface of the die and extends through the package molding, exposing it to the ambient environment. This integration allows for the use of high power devices in dense circuit board applications without increasing the package size or footprint, thus limiting cost increases.

Another notable patent is the semiconductor component package assembly that includes an integral radio frequency and electromagnetic interference (RF/EMI) shield. This assembly features a support member that holds an IC chip and defines an array of conductive leads. An electrically conductive shield is strategically positioned to form an integral RF/EMI barrier between the IC chip and its surroundings. The shield is designed with multiple layers of material, ensuring effective electrical connection to ground leads, enhancing the overall performance of the assembly.

Career Highlights

Jagdish G Belani has had a successful career at National Semiconductor Corporation, where he has been instrumental in developing innovative semiconductor solutions. His work has significantly impacted the efficiency and performance of electronic devices.

Collaborations

Throughout his career, he has collaborated with notable colleagues, including Shahram Mostafazadeh and Satya N Chillara, contributing to various projects that have advanced semiconductor technology.

Conclusion

Jagdish G Belani's contributions to the field of semiconductor technology through his patents and innovations have established him as a key figure in the industry. His work continues to influence the development of high-performance electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…