The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 1986

Filed:

Sep. 26, 1985
Applicant:
Inventors:

Hem P Takiar, San Jose, CA (US);

Jagdish Belani, Cupertino, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
C25D / ;
U.S. Cl.
CPC ...
2042 / ;
Abstract

A system for electroplating metals, such as tin and solder on semiconductor lead frame strips includes a magazine for carrying the lead frames and a separate plating rack for carrying the magazines. The plating rack, which has an insulated surface, includes means for directing a current to the lead frame strips when the magazine is inserted in the plating rack. An electric coupling means is also provided for assuring that the current from the plating rack is evenly distributed among the individual lead frame strips so that uniform plating results. The magazine is suitable for transporting and storing the lead frame strips during assembly of semiconductor components, and it is unnecessary to remove the lead frame strips from the magazine for mounting on the plating rack.


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Takiar, Hem. (1986). System for electroplating molded semiconductor devices (U.S. Patent No. 4595480). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4595480

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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