The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 1997
Filed:
Mar. 01, 1996
Applicant:
Inventors:
Peter M Weiler, Alpine, UT (US);
Jagdish G Belani, Cupertino, CA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257777 ; 257676 ; 257672 ; 257203 ;
Abstract
An integrated circuit package assembly incorporating an electrostatic discharge (ESD) interposer is disclosed. The assembly includes a semiconductor chip including a plurality of chip input/output terminals. The interposer is formed using a substrate which supports the chip and includes an arrangement having a plurality of integrally formed ESD protection circuits for providing ESD protection to predetermined ones of the chip input/output terminals.
Quick Actions:
Weiler, Peter. (1997). Integrated circuit package assemblies including an electrostatic (U.S. Patent No. 5644167). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5644167
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile