Jack Chang Chien

This inventor holds 13 USPTO granted patents, primarily in Semiconductor Packaging. Top assignees: Sandisk Corporation, Sandisk Technologies Inc.. Active years: 2009-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jack Chang Chien. Retrieved from https://idiyas.com/inventor/jack-chang-chien

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 13

% Patents Active = 46.2

Average Co-Inventor Count = 5.6

ph-index = 2

Forward Citations = 16(Granted Patents)

Location History:

Kaoshiung, TW (2009 - 2013)
Shanghai, CN (2013)
Koashiung, TW (2009 - 2014)

Company Filing History:

Sandisk Technologies Inc.

patents

Years Active: 2009-2014

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Areas of Expertise:

Semiconductor

Die Attach Tape

Adhesion Promotion

Over-Molded Memory Cards

Substrate Connections

Redistribution Layer

Thermal Management

Injection Molding

13 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8637972 - Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel (2014-01-28),

2. 8499813 - System for separating a diced semiconductor die from a die attach tape (2013-08-06),

3. 8482139 - Methods of promoting adhesion between transfer molded IC packages and injection molded plastics for creating over-molded memory cards (2013-07-09),

4. 8232145 - Methods of promoting adhesion between transfer molded IC packages and injection molded plastics for creating over-molded memory cards (2012-07-31),

5. 8212360 - Semiconductor die having a redistribution layer (2012-07-03),

6. 7967184 - Padless substrate for surface mounted components (2011-06-28),

7. 7952179 - Semiconductor package having through holes for molding back side of package (2011-05-31),

8. 7939944 - Semiconductor die having a redistribution layer (2011-05-10),

9. 7939382 - Method of fabricating a semiconductor package having through holes for molding back side of package (2011-05-10),

10. 7772047 - Method of fabricating a semiconductor die having a redistribution layer (2010-08-10),

11. 7763980 - Semiconductor die having a distribution layer (2010-07-27),

12. 7615861 - Methods of promoting adhesion between transfer molded IC packages and injection molded plastics for creating over-molded memory cards (2009-11-10),

13. 7611927 - Method of minimizing kerf width on a semiconductor substrate panel (2009-11-03),

Title: Jack Chang Chien: Innovator in Semiconductor Technology

Introduction

Jack Chang Chien is a prominent inventor based in Kaohsiung, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 13 patents. His innovative work focuses on improving the efficiency and effectiveness of semiconductor manufacturing processes.

Latest Patents

Among his latest patents is a groundbreaking design for a two-sided substrate lead connection aimed at minimizing kerf width on a semiconductor substrate panel. This invention ensures electrical isolation of plated electrical terminals while maximizing space on the substrate panel for semiconductor packages. Another notable patent involves a system for separating a diced semiconductor die from a die attach tape. This system features an ejector tool that utilizes a vacuum source to facilitate the ejection of semiconductor dies during the wafer dicing process.

Career Highlights

Jack has worked with notable companies such as SanDisk Corporation and SanDisk Technologies Inc. His experience in these organizations has allowed him to refine his skills and contribute to advancements in semiconductor technology.

Collaborations

Throughout his career, Jack has collaborated with talented individuals, including Hem P Takiar and Chin-Tien Chiu. These partnerships have fostered innovation and have been instrumental in the development of his patented technologies.

Conclusion

Jack Chang Chien's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence advancements in semiconductor manufacturing processes.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]