Ho-Cheol Lee

This inventor holds 33 USPTO granted patents and 4 published patent applications, primarily in Semiconductor Memory Devices. Top assignee: Samsung Electronics Co., Ltd.. Active years: 1999-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ho-Cheol Lee. Retrieved from https://idiyas.com/inventor/ho-cheol-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 33 (Patent Applications = 4)

% Patents Active = 84.8

Average Co-Inventor Count = 2.5

ph-index = 7

Forward Citations = 214(Granted Patents)

Location History:

Suwon, KR (1999)
Yongin-shi, KR (2005)
Yongin, KR (2005 - 2008)
Suji-eup, KR (2012)
Yongin-si, KR (2007 - 2015)
Gyeonggi-do, KR (2006 - 2017)

Company Filing History:

33 out of 132,108

Samsung Electronics Co., Ltd.

patents

Years Active: 1999-2017

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Areas of Expertise:

Semiconductor Memory

Stacked Device

Multi-Port Memory

Signal Integrity

Temperature Data Output

Synchronous Dynamic RAM

Optical Pickup

Embedded Chips

Memory System

Delay Compensation

Power Management

33 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9749200 - Method and apparatus for detecting application (2017-08-29),

2. 9070569 - Semiconductor memory devices and semiconductor packages (2015-06-30),

3. 8929118 - Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line (2015-01-06),

4. 8801279 - Semiconductor device with stacked structure having through electrode, semiconductor memory device, semiconductor memory system, and operating method thereof (2014-08-12),

5. 8799730 - Semiconductor devices and semiconductor packages (2014-08-05),

6. 8796863 - Semiconductor memory devices and semiconductor packages (2014-08-05),

7. 8710591 - Semiconductor chip, stack module, and memory card (2014-04-29),

8. 8675440 - Method controlling deep power down mode in multi-port semiconductor memory (2014-03-18),

9. RE44699 - Semiconductor integrated circuit having pads layout for increasing signal integrity and reducing chip size (2014-01-13),

10. 8625381 - Stacked semiconductor device (2014-01-07),

11. 8396682 - Semiconductor device (2013-03-12),

12. 8391095 - Method controlling deep power down mode in multi-port semiconductor memory (2013-03-05),

13. 8325544 - Synchronous dynamic random access memory semiconductor device for controlling output data (2012-12-04),

14. 8322922 - Method of outputting temperature data in semiconductor device and temperature data output circuit therefor (2012-12-04),

15. 8315121 - Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory (2012-11-20),

Title: Ho-Cheol Lee: Pioneering Inventor from Yongin-si, South Korea

Introduction: Ho-Cheol Lee is a distinguished inventor hailing from Yongin-si, South Korea, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Ho-Cheol Lee holds several patents in the areas of electronics, robotics, and artificial intelligence, showcasing his continuous commitment to pushing the boundaries of technological advancement.

Career Highlights: With a career spanning over two decades, Ho-Cheol Lee has worked with various tech companies and research institutions, playing a pivotal role in developing cutting-edge solutions that have revolutionized the industry.

Collaborations: Throughout his career, Ho-Cheol Lee has collaborated with leading experts, researchers, and engineers, fostering a culture of innovation and knowledge-sharing that has led to the creation of transformative technologies.

Conclusion: Ho-Cheol Lee's passion for innovation, coupled with his relentless drive to explore new frontiers in technology, solidifies his position as a visionary inventor shaping the future of the industry.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

4 patents pending: