Samsung Electronics Co., Ltd.

Ho-Cheol Lee

Chi-Sung Oh

Jung-bae Lee

Dong-Hyuk Lee

Jung-Sik Kim

Nam-Jong Kim

Jang-Woo Ryu

Hyong-Ryol Hwang

Chang-Ho Lee

Chul-woo Lee

Jang-hoon Yoo

Young-Min Lee

Kun-ho Cho

Dae-Sik Kim

Young-Il Kim

Soon-kyo Hong

Han-gu Sohn

Kyung-Woo Nam

Hyo-Joo Ahn

Kyoung-Hwan Kwon

Jin-Kuk Kim

Yun-Hee Shin

Jae-Hoon Kim

Jong-Hun Kim

Jung-Bae Lee

Jin-ho Kim

Dae-Hwan Kim

Kyu-Chan Lee

Uk-Song Kang

Ho-Young Kim

Soo-Young Kim

Seung-tae Jung

Jae-Jin Kim

Hoon Bok Lee

Jong-Wook Park

Ju-hyung Lee

Sang-Kyun Park

Jin-hyoung Kwon

Yun-Young Lee

Han-Gu Sohn

Mi-Jo Kim

Soo-Man Hwang

Hyun-seob Choi

Byong-wook Na

Jung-Soo Ryoo

Kwang-Myeong Jang

Jung-Su Ryu

Sang-beom Hong

Sang-kyu Kang

Jae-Young Seol

Sang-Ig Rho

Sung-Jun Do

Kwang-sup Im

Provided is a method for detecting an application in a wireless communication system. The method includes receiving and inspecting a packet; detecting flows from the packet using a predefined signature; granting a score to each of the detected flows, and summing the granted scores by integrating the detected flows for each application; comparing the summed score of the flows integrated for each application with a preset value; and determining that an application is detected, if the summed score is greater than the preset value.

Method and apparatus for detecting application

A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Semiconductor memory devices and semiconductor packages

A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line

A semiconductor device, memory device, system, and method of using a stacked structure for stably transmitting signals among a plurality of semiconductor layers is disclosed. The device includes at least a first semiconductor chip including a first temperature sensor circuit configured to output first temperature information related to the first semiconductor chip, and at least one through substrate via.

Semiconductor device with stacked structure having through electrode, semiconductor memory device, semiconductor memory system, and operating method thereof

Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.

Semiconductor devices and semiconductor packages

Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV.

Semiconductor chip, stack module, and memory card

A method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors includes controlling the deep power down mode in the multi-port semiconductor memory such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

Method controlling deep power down mode in multi-port semiconductor memory

A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.

Semiconductor integrated circuit having pads layout for increasing signal integrity and reducing chip size

Provided is a stacked semiconductor device including n stacked chips. Each chip includes 'j' corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.

Stacked semiconductor device

A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

Semiconductor device

Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation.

Method of outputting temperature data in semiconductor device and temperature data output circuit therefor

Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.

Synchronous dynamic random access memory semiconductor device for controlling output data

An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels in one-to-one correspondence and that are configured to commonly use the reference voltage generated by the reference voltage generator. Each internal power generator may be configured to receive a fed back internal power voltage, to compare the fed back internal power voltage to the reference voltage, and to generate an internal power voltage based on the comparison. The system further comprises a plurality of channel state detectors that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively detect operation states of the plurality of channels based on separate respective sets of command signals for each channel. The system additional comprises a plurality of internal power controllers that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively control driving capabilities for the internal power voltages according to the detected operation states.

Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory

Growing community of inventors

Yongin-si, South Korea

Ho-Cheol Lee