The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2014

Filed:

Dec. 12, 2007
Applicant:

Ho-cheol Lee, Yongin-si, KR;

Inventor:

Ho-Cheol Lee, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2005.12); H01L 23/49 (2005.12); H01L 23/52 (2005.12); H01L 23/495 (2005.12);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.


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Lee, Ho-Cheol. (2014). Semiconductor integrated circuit having pads layout for increasing signal integrity and reducing chip size (U.S. Patent No. RE44699). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/RE44699

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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