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For the Inventor, By the Inventor

Austin, TX, United States of America

Hemanshu T Vernenker

This inventor holds 18 USPTO granted patents, primarily in Memory Systems. Top assignees: Lattice Semiconductor Corporation, Kilopass Technology, Inc., Motorola Corporation. Active years: 2001-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hemanshu T Vernenker. Retrieved from https://idiyas.com/inventor/hemanshu-t-vernenker

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18

% Patents Active = 77.8

Average Co-Inventor Count = 3.6

ph-index = 5

Forward Citations = 109(Granted Patents)


Location History:

  • Santa Clara, CA (US) (2007 - 2008)
  • Austin, TX (US) (2001 - 2010)

Company Filing History:

goldMedal16 out of 765 
 
Lattice Semiconductor Corporation
 patents
silverMedal1 out of 45 
 
Kilopass Technology, Inc.
 patents
bronzeMedal1 out of 20,290 
 
Motorola Corporation
 patents

Years Active: 2001-2010

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Areas of Expertise:
Integrated Circuits
Variable Data Width
Multi-Port Memory
Bitline Twisting
Memory Testing
Cascadable Memory
Pulse-Generation Circuit
Sense Amplifier Timing
Non-Volatile Memory
Echo Clock Generation
Address Decoding
Feedback Systems
18 patents (USPTO):Explore Patents
1. 7685483 - Design features for testing integrated circuits (2010-03-23),
2. 7539076 - Variable data width memory systems and methods (2009-05-26),
3. 7414913 - Bitline twisting scheme for multiport memory (2008-08-19),
4. 7378879 - Decoding systems and methods (2008-05-27),
5. 7376872 - Testing embedded memory in integrated circuits such as programmable logic devices (2008-05-20),
6. 7342846 - Address decoding systems and methods (2008-03-11),
7. 7317343 - Pulse-generation circuit with multi-delay block and set-reset latches (2008-01-08),
8. 7307912 - Variable data width memory systems and methods (2007-12-11),
9. 7221607 - Multi-port memory systems and methods for bit line coupling (2007-05-22),
10. 7215591 - Byte enable logic for memory (2007-05-08),
11. 7187203 - Cascadable memory (2007-03-06),
12. 7177221 - Initializing memory blocks (2007-02-13),
13. 7177207 - Sense amplifier timing (2007-02-13),
14. 7173851 - 3.5 transistor non-volatile memory cell using gate breakdown phenomena (2007-02-06),
15. 7149129 - Memory output data systems and methods with feedback (2006-12-12),

Title: Hemanshu T Vernenker: Pioneering Innovator in Integrated Circuits Testing

Introduction:

Hemanshu T Vernenker, an accomplished inventor based in Austin, TX, has made significant contributions to the field of integrated circuits testing. With a keen focus on enhancing memory systems and testing capabilities, he has earned recognition for his groundbreaking innovations.

Latest Patents:

Vernenker's latest patents showcase his expertise in designing novel features for testing integrated circuits and developing variable data width memory systems. His ingenuity is evident in inventions such as techniques for doubling memory width without increasing internal data path width or input/output pads.

Career Highlights:

Having amassed an impressive portfolio of 18 patents, Hemanshu T Vernenker has left an indelible mark on the tech industry. His work at esteemed companies like Lattice Semiconductor Corporation and Kilopass Technology, Inc. has been instrumental in advancing cutting-edge technologies in the semiconductor sector.

Collaborations:

Throughout his career, Vernenker has collaborated with industry peers such as Allen White and Margaret Tait. These collaborative efforts have led to the creation of innovative solutions that have revolutionized integrated circuits testing and memory systems design.

Conclusion:

Hemanshu T Vernenker's relentless pursuit of innovation and his passion for pushing the boundaries of technological advancements have cemented his reputation as a pioneering inventor in the field of integrated circuits testing. His contributions continue to inspire future generations of inventors and shape the landscape of the tech industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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