Lattice Semiconductor Corporation

Motorola Corporation

Kilopass Technology, Inc.

Hemanshu T Vernenker

Allen White

Margaret Tait

Christopher Hume

Louis De La Cruz

Nhon Nguyen

Sam Tsai

Tim Swensen

Steve Eplett

Marge Tait

Harry Luan

Glen Arnold Rosendale

John Schadt

John M Callahan

Zheng Chen

Harold Scholz

Larry Fenstermaker

Michael David Fliesler

Mohammed Hasan Taufique

Gregory S Cartney

Zhongshang Liu

Dong-Sun Min

Michael Nelson

Robert Feather

Systems and methods are disclosed herein to provide test features for integrated circuits. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an input signal path adapted to route an address signal for a configurable memory. An input multiplexer, coupled to the input signal path, is controllable to route a first test signal provided via the input signal path for at least one memory configuration that does not use the input signal path for the address signal.

Design features for testing integrated circuits

Systems and methods disclosed herein provide for variable data width memory. For example, in accordance with an embodiment of the present invention, a technique for doubling a width of a memory is disclosed, without having to increase a width of the internal data path or the number of input/output pads.

Variable data width memory systems and methods

A multiport memory in one embodiment of the invention includes a memory cell array, where each column in the array has two exterior complementary bitline pairs and zero, one, or more interior complementary bitline pairs. Across each pair of adjacent columns in the array, the adjacent exterior bitline pairs are associated with the same port in the multiport memory. In addition, within each column, the two exterior bitline pairs have the same, non-zero number of crossovers, and, across each pair of adjacent columns, the exterior bitline pairs have different numbers of crossovers. Furthermore, each column has at least one reference signal line located between the two exterior bitline pairs.

Bitline twisting scheme for multiport memory

Systems and methods are disclosed herein for decoder applications. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a decoder that receives a plurality of input signals and partially decodes the input signals based on their true and complement values to provide a plurality of decoded signals. The decoded signals, for example, may be utilized to control a multiplexer.

Decoding systems and methods

Method and apparatus for the testing of embedded memories in integrated circuits such as programmable logic devices are disclosed. In conjunction with a partial BIST engine, an external tester provides the embedded memories with test vectors. The on-chip partial BIST engine retrieves the test vectors from the embedded memories and compares them to corresponding expected test vectors supplied by the external tester. Based upon the comparison, the on-chip partial BIST engine forms comparison results indicating whether the retrieved test vectors differ from the corresponding expected test vectors. For programmable logic devices, a full BIST engine may be configured in the integrated circuit for generating the test vectors on chip.

Testing embedded memory in integrated circuits such as programmable logic devices

Systems and methods provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal. The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal. An address pre-decoder, coupled to the address register, at least partially decodes the registered address signal to provide a pre-decoded output signal. A wordline driver, coupled to the address pre-decoder, receives a wordline enable signal and the pre-decoded output signal and provides a wordline signal based on the pre-decoded output signal upon assertion of the wordline enable signal.

Address decoding systems and methods

In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and reset signals from different pulse generators operating based on different delayed clock signals from the clock-delay circuitry. In one implementation, the clock-delay circuitry has a partitioned delay block in which different sub-blocks provide different delay functionality to provide the clock-delay circuitry with programmable flexibility.

Pulse-generation circuit with multi-delay block and set-reset latches

Systems and methods provide bit line coupling detection techniques for multi-port memory applications. For example, in accordance with an embodiment of the present invention, a memory includes at least one column of memory having a plurality of memory cells and at least two ports and a dummy column having a dummy memory cell and a first port and a second port. At least one bit line is provided for each port of the columns of memory and the dummy column, with the dummy column adapted to provide a read timing indication by performing a write operation through the first port at substantially the same time as a read operation through the second port.

Multi-port memory systems and methods for bit line coupling

Systems and methods are disclosed herein to provide techniques for writing to certain bits of a word location in a memory. For example, in accordance with an embodiment of the present invention, a method of implementing byte enable logic for a memory is disclosed, with the byte enable logic signals provided on one or more address lines.

Byte enable logic for memory

In accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of memory blocks, and a plurality of continuation routing paths associated with the memory blocks. A plurality of continuation multiplexers, coupled to the continuation routing paths, are adapted to route signals between the memory blocks, between the logic blocks, and/or between the memory blocks and the logic blocks.

Cascadable memory

In accordance with one embodiment of the present invention, a programmable logic device includes at least one block of memory having a plurality of memory cells and a plurality of fuses adapted to provide a first set of signals that determines a first configuration for the at least one block of memory. A plurality of multiplexers are adapted to select the first set of signals from the plurality of fuses to configure the at least one block of memory in the first configuration or a second set of signals to configure the at least one block of memory in a second configuration.

Initializing memory blocks

Systems and methods provide sense amplifier timing techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of memory cells and a sense amplifier that provides a sense amplifier output signal based on data provided by the plurality of memory cells, with the sense amplifier output signal provided under control of a sense amplifier enable signal. A delay control circuit provides a delay to the sense amplifier enable signal based on a value provided by at least one configuration fuse.

Sense amplifier timing

A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.

3.5 transistor non-volatile memory cell using gate breakdown phenomena

Systems and methods provide output data from a memory. For example, in accordance with an embodiment of the present invention, techniques are disclosed for providing glitch-free output data from a memory through feedback of the output data signal.

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Austin, TX, United States of America

Hemanshu T Vernenker