The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2007

Filed:

Feb. 09, 2005
Applicants:

Hemanshu T. Vernenker, Austin, TX (US);

Louis DE LA Cruz, Pflugerville, TX (US);

Allen White, Austin, TX (US);

Inventors:

Hemanshu T. Vernenker, Austin, TX (US);

Louis De La Cruz, Pflugerville, TX (US);

Allen White, Austin, TX (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods provide bit line coupling detection techniques for multi-port memory applications. For example, in accordance with an embodiment of the present invention, a memory includes at least one column of memory having a plurality of memory cells and at least two ports and a dummy column having a dummy memory cell and a first port and a second port. At least one bit line is provided for each port of the columns of memory and the dummy column, with the dummy column adapted to provide a read timing indication by performing a write operation through the first port at substantially the same time as a read operation through the second port.


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