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For the Inventor, By the Inventor

Saratoga, CA, United States of America

Fu-Chieh Hsu

USPTO Granted Patents = 61

Average Co-Inventor Count = 1.8

ph-index = 28

Forward Citations = 3,971(Granted Patents)


Inventors with similar research interests:


Location History:

  • Cupertino, CA (US) (1988 - 1989)
  • Saratogo, CA (US) (1996)
  • Saratoga, CA (US) (1991 - 2009)

Company Filing History:

goldMedal45 out of 67 
 
Monolithic System Technology, Inc.
 patents
silverMedal5 out of 1,264 
 
Integrated Device Technology, Inc.
 patents
bronzeMedal3 out of 79 
 
Mosys, Inc.
 patents
4. 2 out of 5 
 
Knights Technology, Inc.
 patents
5. 1 out of 13 
 
Myson Technology Inc.
 patents
6. 1 out of 9,638 
 
Hewlett-packard Company
 patents
7. 1 out of 6 
 
Monolithic Systems, Inc.
 patents
8. 1 out of 3 
 
Monolithic Systems Technology, Inc.
 patents
9. 1 out of 2 
 
Monlithic System Technology, Inc.
 patents
10. 2 out of 832,680 
Other
 patents
where one patent can have more than one assignee

Years Active: 1988-2009

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61 patents (USPTO):
1. 7634707 - Error detection/correction method (2009-12-15),
2. 7353438 - Transparent error correcting memory (2008-04-01),
3. 7323379 - Fabrication process for increased capacitance in an embedded DRAM memory (2008-01-29),
4. 7206913 - High speed memory system (2007-04-17),
5. 7056785 - Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same (2006-06-06),
6. 7051264 - Error correcting memory and method of operating same (2006-05-23),
7. 6964895 - Method of fabricating vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region (2005-11-15),
8. 6913964 - Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region (2005-07-05),
9. 6841821 - Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same (2005-01-11),
10. 6808169 - Non-volatile memory with crown electrode to increase capacitance between control gate and floating gate (2004-10-26),
11. 6784048 - Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage (2004-08-31),
12. 6754746 - Memory array with read/write methods (2004-06-22),
13. 6744676 - DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same (2004-06-01),
14. 6717864 - Latched sense amplifiers as high speed memory in a memory system (2004-04-06),
15. 6686624 - Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region (2004-02-03),

Title: Innovations and Achievements of Fu-Chieh Hsu

Introduction

Fu-Chieh Hsu is a prominent inventor located in Saratoga, California. With an impressive portfolio comprising 61 patents, Hsu has significantly contributed to the fields of error detection and correction technologies. His innovative methods have had a transformative impact on memory systems and data integrity.

Latest Patents

Hsu's latest patents include an advanced error detection/correction method and a memory system with transparent error correction circuitry. The error detection/correction method entails generating a complete EDC code in response to a data packet and distributing it among the data packet to create a plurality of bytes. Each byte contains a data portion and an EDC code portion, which are stored and retrieved from a memory module for thorough error checking and correction.

The transparent error correcting memory system, on the other hand, is designed to provide full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. This system incorporates a semiconductor memory that ensures single-bit errors in test data patterns are corrected efficiently, making multiple-bit faults 100% detectable.

Career Highlights

Throughout his career, Fu-Chieh Hsu has worked with several esteemed companies, including Monolithic System Technology, Inc. and Integrated Device Technology, Inc. His vast experience in these roles has undoubtedly enriched his expertise in innovative memory technologies and error correction methods.

Collaborations

In his professional journey, Hsu has collaborated with notable individuals such as Wingyu Leung and Winston Lee. These collaborations have likely fostered an exchange of ideas and insights that have contributed to his success as an inventor.

Conclusion

Fu-Chieh Hsu’s remarkable achievements and patented inventions highlight his pivotal role in advancing error detection and correction technologies. His work not only reflects a commitment to innovation but also exemplifies the impact of collaborative efforts in the tech industry. With a legacy of 61 patents to his name, Hsu remains a significant figure in the realm of technology and invention.

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