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Sunnyvale, CA, United States of America

Monolithic System Technology, Inc.

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USPTO Granted Patents = 72

% Expired Patents = 15.3

Trademarks = 1

Forward Citations = 4,089

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10 inventors (with patents filed for the assignee):

Wingyu Leung (57 out of 98 patents)

Fu-Chieh Hsu (47 out of 61 patents)

Winston Lee (7 out of 11 patents)

4. Wing Yu Leung (5 out of 5 patents)

5. Jui-Pin Tang (3 out of 3 patents)

6. Jae-Kwang Sim (2 out of 2 patents)

7. Kit Sang Tam (2 out of 17 patents)

8. Jeffrey J Lin (2 out of 2 patents)

9. Chenming Hu (1 out of 155 patents)

10. Jae-Hong Jeong (1 out of 1 patent)

Core Competencies:

Non-Volatile Memory

DRAM Cells

High-Speed Read-Write

Floating-Body DRAM

Memory Array

Sense Amplifiers

Cache Memory

Temperature Adaptive Refresh

Data Retention

Memory Redundancy

Semiconductor Packaging

Circuit Module Architecture

72 patents: Sort by Forward Citations

1. 7275200 - Transparent error correcting memory that supports partial-word write (2007-09-25),

2. 7274618 - Word line driver for DRAM embedded in a logic process (2007-09-25),

3. 7206913 - High speed memory system (2007-04-17),

4. 7056785 - Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same (2006-06-06),

5. 7051264 - Error correcting memory and method of operating same (2006-05-23),

6. 6964895 - Method of fabricating vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region (2005-11-15),

7. 6913964 - Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region (2005-07-05),

8. 6898140 - Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors (2005-05-24),

9. 6841821 - Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same (2005-01-11),

10. 6808169 - Non-volatile memory with crown electrode to increase capacitance between control gate and floating gate (2004-10-26),

11. 6795364 - Method and apparatus for lengthening the data-retention time of a DRAM device in standby mode (2004-09-21),

12. 6784048 - Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage (2004-08-31),

13. 6754746 - Memory array with read/write methods (2004-06-22),

14. 6751157 - Method and apparatus for completely hiding refresh operations in a DRAM device using clock division (2004-06-15),

15. 6744676 - DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same (2004-06-01),

Company Overview

Monolithic System Technology, Inc., based in Sunnyvale, California, specializes in advanced memory technology solutions. The company focuses on developing innovative non-volatile memory systems, including high-speed read-write capabilities and floating-body DRAM. Their expertise extends to memory arrays, sense amplifiers, and cache memory, with a commitment to enhancing performance through temperature adaptive refresh techniques. MST's cutting-edge technologies aim to address the evolving demands of data storage and processing in various applications.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 27 2026

72 Patents

#71 in Sunnyvale, CA

#1,205 in California

#5,110 in US

#10,400 in the World

Sunnyvale, CA, United States of America

Monolithic System Technology, Inc.

Forward Citations = 4,089

10 inventors:

Wingyu Leung (57 out of 98 patents)

Fu-Chieh Hsu (47 out of 61 patents)

Winston Lee (7 out of 11 patents)

4. Wing Yu Leung (5 out of 5 patents)

5. Jui-Pin Tang (3 out of 3 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Monolithic System Technology, Inc.. Retrieved from https://idiyas.com/company/monolithic-system-technology

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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