The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
Aug. 25, 2004
Fu-chieh Hsu, Saratoga, CA (US);
Wingyu Leung, Cupertino, CA (US);
Fu-Chieh Hsu, Saratoga, CA (US);
Wingyu Leung, Cupertino, CA (US);
Monolithic System Technology, Inc., Sunnyvale, CA (US);
Abstract
A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.