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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Eyal En Gad

This inventor holds 33 USPTO granted patents and 11 published patent applications, primarily in Error Correction Coding. Top assignee: Micron Technology Incorporated. Active years: 2019-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Eyal En Gad. Retrieved from https://idiyas.com/inventor/eyal-en-gad

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 33 

% Patents Active = 100.0

Average Co-Inventor Count = 3.2

ph-index = 2

Forward Citations = 10(Granted Patents)


Location History:

  • Santa Clara, CA (US) (2019 - 2024)
  • Highland, CA (US) (2022 - 2024)

Company Filing History:

goldMedal33 out of 39,176 
 
Micron Technology Incorporated
 patents

Years Active: 2019-2026

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Areas of Expertise:
Syndrome Decoding
Error Decoding
Bit-Flipping Techniques
Voltage Scaling
Low-Density Parity-Check Codes
Dynamic Thresholds
Memory Efficiency
Power Efficiency
Iterative Parameter Updating
Data Encoding
Error Correction
Selective Reliability Update
33 patents (USPTO):Explore Patents
1. 12737257 - Syndrome decoding system (2026-09-15),
2. 12730714 - Hard information decoder aided by a soft information decoder (2026-09-08),
3. 12712043 - VOLTAGE SCALING BASED ON ERROR RATE (2026-08-18),
4. 12712042 - VOLTAGE SCALING BASED ON ERROR RATE (2026-08-18),
5. 12705134 - Selective reliability update for error decoding (2026-08-11),
6. 12700876 - Data encoding and decoding schemes (2026-08-04),
7. 12699630 - Syndrome calculation (2026-08-04),
8. 12683630 - Error decoding with iterative parameter updating (2026-07-14),
9. 12656975 - Separation of parity columns in bit-flip decoding of low-density parity-check codes with pipelining and column parallelism (2026-06-16),
10. 12647134 - Shaped parity bit recovery via bit-flipping (2026-06-02),
11. 12645535 - Decoding data using a constrained bit-flipping technique (2026-06-02),
12. 12633943 - Row weight adjustment in two-level low-density parity-check (LDPC) error correction (2026-05-19),
13. 12517674 - Dynamic bit flip thresholds based on soft bit and match bit (2026-01-06),
14. 12511059 - Power efficient codeword scrambling in a non-volatile memory device (2025-12-30),
15. 12437788 - Syndrome decoding system (2025-10-07),

Title: The Innovative Journey of Eyal En Gad

Introduction: Eyal En Gad is a visionary inventor based in Santa Clara, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Eyal En Gad holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his commitment to pushing the boundaries of what is possible.

Career Highlights: With a career spanning over two decades, Eyal En Gad has worked with leading tech companies, research institutions, and universities to develop cutting-edge solutions that have revolutionized the industry.

Collaborations: Throughout his career, Eyal En Gad has collaborated with top engineers, scientists, and researchers, fostering a culture of innovation and creativity that has led to numerous successful projects and inventions.

Conclusion: Eyal En Gad's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and entrepreneurs in the ever-evolving world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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