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For the Inventor, By the Inventor

San Jose, CA, United States of America

Enrique Musoll

This inventor holds 69 USPTO granted patents and 4 published patent applications and 1 EPO patent, primarily in Packet Processing (CPC class G06F). Top assignees: Astera Labs, Inc., Mips Technologies, Inc., Cavium, Inc.. Active years: 2006-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Enrique Musoll. Retrieved from https://idiyas.com/inventor/enrique-musoll

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 69 

% Patents Active = 81.2


Average Co-Inventor Count = 2.3

ph-index = 10

Forward Citations = 332(Granted Patents)

Forward Citations (Not Self Cited) = 271(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:

goldMedal24 out of 35 
 
Astera Labs, Inc.
 patents
silverMedal20 out of 271 
 
Mips Technologies, Inc.
 patents
bronzeMedal9 out of 448 
 
Cavium, Inc.
 patents
4. 9 out of 1,233 
 
Marvell Asia Pte., Ltd.
 patents
5. 3 out of 3 
 
Consentry Networks, Inc.
 patents
6. 1 out of 1 
 
Asiera Labs, Inc.
 patent
7. 3 out of 834,453 
Other
 patents

Years Active: 2006-2026

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Areas of Expertise:
Packet Processing
Low-Latency Retimer
Memory Control
CXL HDM Decoding
Metadata Storage
Power Consumption
Path-Coordinated Flow
Configurable Aggregation
Seamless Clock Switchover
HPA Generator
Datapath Subsystem
Mesh Architecture
69 patents (USPTO):Explore Patents
1. 12730751 - Metadata-caching integrated circuit device (2026-09-08),
2. 12596612 - Virtual metadata storage with decode-alias mitigation (2026-04-07),
3. 12579076 - CXL HDM decoding sequencing for reduced area and power consumption (2026-03-17),
4. 12542646 - Configurable-aggregation retimer with lane-dedicated controllers (2026-02-03),
5. 12505039 - Early potential HPA generator (2025-12-23),
6. 12489590 - Retimer with path-coordinated flow-rate compensation (2025-12-02),
7. 12323164 - Capacity-expanding memory control component (2025-06-03),
8. 12298925 - Packet processing system, method and device utilizing a port client chain (2025-05-13),
9. 12277350 - Virtual metadata storage (2025-04-14),
10. 12277002 - Low-latency retimer with seamless clock switchover (2025-04-14),
11. 12143288 - Low-latency signaling-link retimer (2024-11-12),
12. 12095480 - Capacity-expanding memory control component (2024-09-17),
13. 12067266 - CXL HDM decoding sequencing for reduced area and power consumption (2024-08-20),
14. 12061793 - Capacity-expanding memory control component (2024-08-13),
15. 12032479 - Metadata-caching integrated circuit device (2024-07-09),

Title: The Innovative Mind of Enrique Musoll

Introduction: Enrique Musoll is a visionary inventor based in San Jose, California. His passion for creating groundbreaking solutions has led to numerous patents and collaborations in the tech industry.

Latest Patents: Enrique Musoll holds several patents in the fields of artificial intelligence, renewable energy, and consumer electronics. His most recent patent focuses on a cutting-edge smart home technology that integrates seamlessly with everyday devices.

Career Highlights: With a background in engineering and computer science, Enrique Musoll has worked for leading tech companies in Silicon Valley. His expertise in product development and innovation has been instrumental in bringing revolutionary ideas to life.

Collaborations: Enrique Musoll has collaborated with top researchers and engineers from renowned universities and research institutions. His ability to work across disciplines has resulted in pioneering projects that push the boundaries of technology.

Conclusion: Enrique Musoll's dedication to innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors. His impact on the tech industry is profound, and his legacy as a forward-thinker is sure to endure for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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