For the Inventor, By the Inventor

Enter assignee name

Santa Clara, CA, United States of America

Astera Labs, Inc.

USPTO Granted Patents = 35

Trademarks = 1

Forward Citations = 21

Loading Chart...

Loading Chart...

26 inventors (with patents filed for the assignee):

Enrique Musoll (24 out of 69 patents)

Subbarao Arumilli (18 out of 25 patents)

Ken (Keqin) Han (17 out of 18 patents)

4. Pulkit Khandelwal (15 out of 21 patents)

5. Casey Morrison (14 out of 18 patents)

6. Anh T Tran (14 out of 34 patents)

7. Chi Feng (10 out of 11 patents)

8. Charan Enugala (8 out of 9 patents)

9. Jitendra Mohan (8 out of 43 patents)

10. Vikas Khandelwal (8 out of 9 patents)

11. Vivek Trivedi (6 out of 13 patents)

12. Nirav Ishwarbhai Patel (3 out of 3 patents)

13. Yiqi Tang (2 out of 54 patents)

14. Dhairya Bapodra (2 out of 2 patents)

15. Hemant Vinchure (1 out of 5 patents)

Core Competencies:

Metadata-Caching

Memory Control

Low-Latency Retimer

Power Distribution

CXL HDM Decoding

Capacity-Expanding

Virtual Metadata Storage

Crosstalk Reduction

High-Speed DIMM

Data Logging Engine

Configurable-Aggregation

SSD Memory Expansion

35 patents: Sort by Forward Citations

1. 12754866 - Smart cable with heterogenous primary/sideband communication channels (2026-10-06),

2. 12730751 - Metadata-caching integrated circuit device (2026-09-08),

3. 12724667 - Memory control component with split auxiliary channel (2026-09-01),

4. 12713936 - CROSS-MESH POWER DISTRIBUTION LAYOUT WITH LOW LOOP INDUCTANCE AND METHOD OF MANUFACTURE (2026-08-18),

5. 12652750 - Interlocking structure for crosstalk reduction and method of manufacture (2026-06-09),

6. 12650770 - Optimizing latency of read transactions with metadata update in memory expansion devices (2026-06-09),

7. 12596612 - Virtual metadata storage with decode-alias mitigation (2026-04-07),

8. 12585850 - Cascaded-scenario logic analyzer (2026-03-24),

9. 12579076 - CXL HDM decoding sequencing for reduced area and power consumption (2026-03-17),

10. 12542646 - Configurable-aggregation retimer with lane-dedicated controllers (2026-02-03),

11. 12505039 - Early potential HPA generator (2025-12-23),

12. 12489590 - Retimer with path-coordinated flow-rate compensation (2025-12-02),

13. 12393350 - SSD-form-factor memory-expansion cartridge with field-replaceable DRAM modules (2025-08-19),

14. 12367168 - High-speed DIMM slot terminator (2025-07-22),

15. 12327135 - Retimer with host-interactive data logging engine (2025-06-10),

Astera Labs, Inc. is a technology company based in Santa Clara, California, specializing in high-performance semiconductor solutions. The company focuses on developing innovative products for data-centric applications, particularly in the fields of data center, cloud computing, and artificial intelligence. Astera Labs aims to enhance the efficiency and performance of data transmission and processing, providing advanced solutions that cater to the evolving needs of modern computing environments.

Profile summary based on public USPTO records.

Company Badge

USPTO Data Jan 1 1976 - Oct 6 2026

35 Patents

#100 in Santa Clara, CA

#2,306 in California

#9,740 in US

#19,148 in the World

Santa Clara, CA, United States of America

Astera Labs, Inc.

Forward Citations = 21

26 inventors:

Enrique Musoll (24 out of 69 patents)

Subbarao Arumilli (18 out of 25 patents)

Ken (Keqin) Han (17 out of 18 patents)

4. Pulkit Khandelwal (15 out of 21 patents)

5. Casey Morrison (14 out of 18 patents)

Please report any incorrect information to [email protected]

Loading…