For the Inventor, By the Inventor

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Santa Clara, CA, United States of America

Astera Labs, Inc.

Calculating rank

USPTO Granted Patents = 38

Trademarks = 1

Forward Citations = 22

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30 inventors (with patents filed for the assignee):

Enrique Musoll (26 out of 71 patents)

Subbarao Arumilli (19 out of 26 patents)

Ken (Keqin) Han (18 out of 19 patents)

4. Pulkit Khandelwal (16 out of 22 patents)

5. Casey Morrison (15 out of 19 patents)

6. Anh T Tran (14 out of 34 patents)

7. Chi Feng (11 out of 12 patents)

8. Jitendra Mohan (10 out of 45 patents)

9. Charan Enugala (9 out of 10 patents)

10. Vikas Khandelwal (9 out of 10 patents)

11. Vivek Trivedi (7 out of 14 patents)

12. Nirav Ishwarbhai Patel (3 out of 3 patents)

13. Justina Provine (3 out of 3 patents)

14. Yiqi Tang (2 out of 54 patents)

15. Hemant Vinchure (2 out of 6 patents)

Core Competencies:

Metadata-Caching

Memory Control

Low-Latency Retimer

Power Distribution

CXL HDM Decoding

Capacity-Expanding

Virtual Metadata Storage

Crosstalk Reduction

High-Speed DIMM

Data Logging Engine

Configurable-Aggregation

SSD Memory Expansion

38 patents: Sort by Forward Citations

1. 12775568 - Switching device with in-transit-compute function (2026-10-27),

2. 12769644 - Free block address management for compressed data storage (2026-10-20),

3. 12761688 - Low-latency retimer with seamless clock switchover (2026-10-13),

4. 12754866 - Smart cable with heterogenous primary/sideband communication channels (2026-10-06),

5. 12730751 - Metadata-caching integrated circuit device (2026-09-08),

6. 12724667 - Memory control component with split auxiliary channel (2026-09-01),

7. 12713936 - CROSS-MESH POWER DISTRIBUTION LAYOUT WITH LOW LOOP INDUCTANCE AND METHOD OF MANUFACTURE (2026-08-18),

8. 12652750 - Interlocking structure for crosstalk reduction and method of manufacture (2026-06-09),

9. 12650770 - Optimizing latency of read transactions with metadata update in memory expansion devices (2026-06-09),

10. 12596612 - Virtual metadata storage with decode-alias mitigation (2026-04-07),

11. 12585850 - Cascaded-scenario logic analyzer (2026-03-24),

12. 12579076 - CXL HDM decoding sequencing for reduced area and power consumption (2026-03-17),

13. 12542646 - Configurable-aggregation retimer with lane-dedicated controllers (2026-02-03),

14. 12505039 - Early potential HPA generator (2025-12-23),

15. 12489590 - Retimer with path-coordinated flow-rate compensation (2025-12-02),

Company Overview

Astera Labs, Inc. is a technology company based in Santa Clara, California, specializing in high-performance semiconductor solutions. The company focuses on developing innovative products for data-centric applications, particularly in the fields of data center, cloud computing, and artificial intelligence. Astera Labs aims to enhance the efficiency and performance of data transmission and processing, providing advanced solutions that cater to the evolving needs of modern computing environments.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 27 2026

38 Patents

#94 in Santa Clara, CA

#2,133 in California

#9,035 in US

#17,870 in the World

Santa Clara, CA, United States of America

Astera Labs, Inc.

Forward Citations = 22

30 inventors:

Enrique Musoll (26 out of 71 patents)

Subbarao Arumilli (19 out of 26 patents)

Ken (Keqin) Han (18 out of 19 patents)

4. Pulkit Khandelwal (16 out of 22 patents)

5. Casey Morrison (15 out of 19 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Astera Labs, Inc.. Retrieved from https://idiyas.com/company/astera-labs

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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