The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2026
Filed:
Feb. 10, 2023
Astera Labs, Inc., Santa Clara, CA (US);
Hemant Vinchure, San Jose, CA (US);
Anh T. Tran, Elk Grove, CA (US);
Ken (Keqin) Han, Fremont, CA (US);
Astera Labs, Inc., San Jose, CA (US);
Abstract
A chip-embedded logic analyzer autonomously sequences between logic analysis scenarios, dynamically revising match criteria and match-responsive behavior as match conditions for each successive scenario are met. Through this cascading-scenario operation, the logic analyzer may log selected debug vectors as and/or after complex sequences of device conditions unfold, enabling substantially more targeted and sophisticated operational debugging than conventional trigger-and-log analyzers.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile