The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2026
Filed:
Apr. 30, 2024
Applicant:
Astera Labs, Inc., Santa Clara, CA (US);
Inventors:
Abhinaya Easwari Mohan, San Jose, CA (US);
Zengji Zhao, Sunnyvale, CA (US);
Yiqi Tang, Allen, TX (US);
Assignee:
Astera Labs, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2026.01); H05K 1/02 (2006.01); H05K 3/46 (2006.01); H10W 42/20 (2026.01); H10W 70/685 (2026.01); H05K 1/181 (2026.01); H05K 3/04 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0224 (2013.01); H05K 3/4602 (2013.01); H10W 42/20 (2026.01); H10W 70/685 (2026.01); H05K 1/181 (2013.01); H05K 3/041 (2013.01); H05K 2201/0723 (2013.01);
Abstract
An electronic system having a mounting substrate with a plurality of layers. The mounting substrate combines an upper shield structure and a lower shield structure to form an interlocking shielding structure to reduces crosstalk interference and improve return loss and insertion loss for high-speed serial communication circuits. The upper shield structure and the lower shield structure have a series of grounded reference shields that reduce unwanted electrical signal interferences.