The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2025
Filed:
Nov. 09, 2023
Astera Labs, Inc., Santa Clara, CA (US);
Jitendra Mohan, Santa Clara, CA (US);
Subbarao Arumilli, Cupertino, CA (US);
Charan Enugala, Newark, CA (US);
Chi Feng, San Jose, CA (US);
Ken (Keqin) Han, Fremont, CA (US);
Pulkit Khandelwal, Cupertino, CA (US);
Vikas Khandelwal, San Jose, CA (US);
Casey Morrison, San Jose, CA (US);
Enrique Musoll, San Jose, CA (US);
Vivek Trivedi, Fremont, CA (US);
Astera Labs, Inc., Santa Clara, CA (US);
Abstract
A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.