The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Jul. 18, 2022
Applicant:

Astera Labs, Inc., Santa Clara, CA (US);

Inventors:

Enrique Musoll, San Jose, CA (US);

Anh Thien Tran, Elk Grove, CA (US);

Assignee:

Astera Labs, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 1/3234 (2019.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 1/3275 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01);
Abstract

A total number V of virtual host-managed device memory (HDM) decoder configurations are generated for the same total number V of HDM memory regions attached to a non-host computing device. Each virtual HDM decoder configuration in the virtual HDM decoder configurations corresponds to a respective HDM memory region in the HDM memory regions. A proper subset of one or more virtual HDM decoder configurations is selected from among the virtual HDM decoder configurations to configure one or more physical HDM decoders of a total number P of the non-host computing device into one or more virtual HDM decoders. The one or more physical HDM decoders configured as one or more virtual HDM decoders are applied to translate a host physical address (HPA) received from a host computing device in a memory access transaction involving the host computing device and the non-host computing device.


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