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For the Inventor, By the Inventor

Austin, TX, United States of America

David L DeMaris

USPTO Granted Patents = 12

Average Co-Inventor Count = 4.8

ph-index = 3

Forward Citations = 48(Granted Patents)


Location History:

  • Essex Junction, VT (US) (2007)
  • Austin, TX (US) (2008 - 2014)

Company Filing History:

goldMedal12 out of 164,108 
 
International Business Machines Corporation
 patents

Years Active: 2007-2014

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12 patents (USPTO):
1. 8863044 - Layout assessment method and system (2014-10-14),
2. 8751980 - Automatic wafer data sample planning and review (2014-06-10),
3. 8667427 - Method of optimization of a manufacturing process of an integrated circuit layout (2014-03-04),
4. 8661370 - Optimization of a manufacturing process of an integrated circuit layout (2014-02-25),
5. 8234603 - Method for fast estimation of lithographic binding patterns in an integrated circuit layout (2012-07-31),
6. 8201132 - System and method for testing pattern sensitive algorithms for semiconductor design (2012-06-12),
7. 7685544 - Testing pattern sensitive algorithms for semiconductor design (2010-03-23),
8. 7552417 - System for search and analysis of systematic defects in integrated circuits (2009-06-23),
9. 7415695 - System for search and analysis of systematic defects in integrated circuits (2008-08-19),
10. 7404174 - method for generating a set of test patterns for an optical proximity correction algorithm (2008-07-22),
11. 7353472 - System and method for testing pattern sensitive algorithms for semiconductor design (2008-04-01),
12. 7284230 - System for search and analysis of systematic defects in integrated circuits (2007-10-16),

Title: The Innovations of David L DeMaris

Introduction

David L DeMaris is a prominent inventor based in Austin, TX, known for his significant contributions to the field of semiconductor technology. With a total of 12 patents to his name, he has made remarkable advancements that have influenced the industry.

Latest Patents

Among his latest patents is the "Layout assessment method and system," which involves assessing candidate layout patterns using a sparse pattern dictionary. This method determines sparse coefficients for each candidate pattern, reconstructs the respective candidate pattern, and identifies reconstruction errors. Patterns exceeding a certain error threshold can be flagged for further review. Additionally, he has developed a patent titled "Automatic wafer data sample planning and review," which outlines a method for constructing masks used in semiconductor device manufacturing. This method involves selecting shapes from a set and forming clusters based on specific criteria.

Career Highlights

David L DeMaris has built a successful career at International Business Machines Corporation (IBM), where he has been instrumental in driving innovation in semiconductor manufacturing processes. His work has not only advanced technology but has also contributed to the efficiency and effectiveness of manufacturing practices.

Collaborations

Throughout his career, David has collaborated with notable colleagues, including William C Leipold and Daniel Nelson Maynard. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas.

Conclusion

David L DeMaris stands out as a key figure in the realm of semiconductor technology, with a proven track record of innovation and collaboration. His contributions continue to shape the future of the industry.

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