International Business Machines Corporation

David L DeMaris

William C Leipold

Daniel Nelson Maynard

Maria Gabrani

Maharaj Mukherjee

Mark Alan Lavin

Michael E Scaman

Timothy G Dunham

Bette L Bergman Reuter

Shi Zhong

Nathalie Casati

Ekaterina Volkova

Alan Edward Rosenbluth

Kehan Tian

Saeed Reza Bagheri

David Osmond Melville

Ronald Peter Luijten

Virginia Estellers Casas

Frank De Morsier

Candidate layout patterns can be assessed using a sparse pattern dictionary of known design layout patterns by determining sparse coefficients for each candidate pattern, reconstructing the respective candidate pattern, and determining reconstruction error. Any pattern with reconstruction error over a threshold value can be flagged. Compressive sampling can be employed, such as by projecting each candidate pattern onto a random line or a random matrix. The dictionary can be built by determining sparse coefficients of known patterns and respective basis function sets using matching pursuit, variants of SVD, and/or other techniques.

Layout assessment method and system

A method of constructing a mask for use in semiconductor device manufacturing is disclosed. A first shape that is related to mask construction is selected from a set of shapes. A second shape related to the mask construction is selected from the set of shapes. The first shape and the second shape are represented using a first shape vector and a second shape vector, respectively. A cluster is formed that includes the first shape and the second shape when the first shape vector and the second shape vector are within a selected criterion.

Automatic wafer data sample planning and review

A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.

Method of optimization of a manufacturing process of an integrated circuit layout

Optimization of a manufacturing process of an integrated circuit layout

The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate &#x3b8;of spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate &#x3b8;, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate &#x3b8;, and a total energy entropy factor comprising total energy entropy of said diffraction orders. The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1. The value of the lithographic difficulty metric may be used to identify patterns in a design layout that are binding patterns in an optimization computation. The lithographic difficulty metric may be used to design integrated circuits that have good, relatively easy-to-print characteristics.

Method for fast estimation of lithographic binding patterns in an integrated circuit layout

A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

System and method for testing pattern sensitive algorithms for semiconductor design

A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

Testing pattern sensitive algorithms for semiconductor design

Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.

System for search and analysis of systematic defects in integrated circuits

A method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.

method for generating a set of test patterns for an optical proximity correction algorithm

Disclosed is a method of locating systematic defects in integrated circuits. Extracting and index processing of a circuit design and feature searching are performed. During extracting and index processing, a window grid for the circuit design is established and basis patterns are merged with shapes within each. Shapes in each window are transformed into feature vectors by finding intersections between basis patterns and shapes. Feature vectors are clustered to produce an index of feature vectors. During feature searching, a defect region window of the circuit layout is identified and basis patterns are merged with shapes in the defect region window. Shapes in the defect region window are transformed into defect vectors by finding intersections between basis patterns and shapes. Feature vectors similar to the defect vector are found using representative feature vectors from the index of feature vectors. Similarities and differences between defect vectors and feature vectors are analyzed.

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Austin, TX, United States of America

David L DeMaris