The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2009

Filed:

Jun. 04, 2008
Applicants:

Bette L. Bergman Reuter, Essex Junction, VT (US);

David L. Demaris, Austin, TX (US);

Mark A. Lavin, Katonah, NY (US);

William C. Leipold, Enosburg Falls, VT (US);

Daniel N. Maynard, Craftsbury Common, VT (US);

Maharaj Mukherjee, Wappingers Falls, VT (US);

Inventors:

Bette L. Bergman Reuter, Essex Junction, VT (US);

David L. DeMaris, Austin, TX (US);

Mark A. Lavin, Katonah, NY (US);

William C. Leipold, Enosburg Falls, VT (US);

Daniel N. Maynard, Craftsbury Common, VT (US);

Maharaj Mukherjee, Wappingers Falls, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.


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