Chung S Wang

This inventor holds 12 USPTO granted patents. Top assignees: Vlsi Technology, Inc., Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 1993-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chung S Wang. Retrieved from https://idiyas.com/inventor/chung-s-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 12

% Patents Active = 91.7

Average Co-Inventor Count = 3.7

ph-index = 9

Forward Citations = 177(Granted Patents)

Company Filing History:

8 out of 1,083

Vlsi Technology, Inc.

patents

4 out of 42,872

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

Years Active: 1993-2015

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12 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9012967 - 1T MIM memory for embedded RAM application in soc (2015-04-21),

2. 8148223 - 1T MIM memory for embedded ram application in soc (2012-04-03),

3. 7994032 - Method of making deep junction for electrical crosstalk reduction of an image sensor (2011-08-09),

4. 7791170 - Method of making a deep junction for electrical crosstalk reduction of an image sensor (2010-09-07),

5. 5631485 - ESD and hot carrier resistant integrated circuit structure (1997-05-20),

6. 5496751 - Method of forming an ESD and hot carrier resistant integrated circuit (1996-03-05),

7. 5444003 - Method and structure for creating a self-aligned bicmos-compatible (1995-08-22),

8. 5411906 - Method of fabricating auxiliary gate lightly doped drain (AGLDD) (1995-05-02),

9. 5340761 - Self-aligned contacts with gate overlapped lightly doped drain (goldd) (1994-08-23),

10. 5288652 - BICMOS-compatible method for creating a bipolar transistor with (1994-02-22),

11. 5227320 - Method for producing gate overlapped lightly doped drain (GOLDD) (1993-07-13),

12. 5196357 - Method of making extended polysilicon self-aligned gate overlapped (1993-03-23),

Title: Innovations of Chung S. Wang

Introduction

Chung S. Wang is a prominent inventor based in Fremont, CA (US). He has made significant contributions to the field of embedded memory technologies, holding a total of 12 patents. His work has been instrumental in advancing the capabilities of system-on-chip (SoC) applications.

Latest Patents

One of his latest patents is for a 1T MIM memory designed for embedded RAM applications in SoC. This innovative device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors, while the first dielectric layer embeds first and second conductive plugs that electrically connect the transistors. The second dielectric layer features a plurality of capacitor openings that expose the first conductive plugs. The capacitors consist of bottom plates disposed in the capacitor openings, which connect the first conductive plugs, along with capacitor dielectric layers overlying the bottom plates. A top plate, which includes a top plate opening, is positioned over the capacitor dielectric layers, exposing the second dielectric layer and is shared by the capacitors.

Career Highlights

Chung S. Wang has worked with notable companies such as VLSI Technology, Inc. and Taiwan Semiconductor Manufacturing Company Ltd. His experience in these organizations has allowed him to refine his expertise in semiconductor technologies and embedded memory systems.

Collaborations

Throughout his career, Chung has collaborated with esteemed colleagues, including Ying T. Loh and Shou-Gwo Wuu. These partnerships have contributed to the successful development of innovative technologies in the semiconductor industry.

Conclusion

Chung S. Wang's contributions to embedded memory technology and his extensive patent portfolio highlight his role as a leading inventor in the field. His work continues to influence advancements in semiconductor applications, showcasing the importance of innovation in technology.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]