Bicmos-compatible method for creating a bipolar transistor with

Abstract

A bipolar transistor is fabricated in a CMOS-compatible process with a laterally graded emitter structure that is fabricated in a 'top-down' implant process. The laterally graded emitter decreases electric field intensities in the emitter-base junction under reverse bias, thus reducing hot carrier generation and improving emitter-base junction breakdown voltage. High current gain is further maintained by establishing sharply defined emitter-base junctions. During fabrication a blocking layer and overlying cap layer are formed in an inverted 'T' shape over a desired emitter window region. Lateral projection of the cap ledges are used to define the laterally graded emitter width, while the distance separating the cap ledges defines the width of the central emitter region. The central emitter region is implanted and driven-in to a desired depth, after which the protective cap is removed. The entire emitter window region is then implanted with a like polarity dopant of lesser dosage, which dopant is then driven-in to form laterally graded emitter junctions of a desired depth. A BiCMOS integrated circuit may be fabricated with bipolar transistors of either polarity and with MOS transistors of either polarity, using substantially the same process steps. The resultant MOS devices have lightly doped drain regions to enhance MOS hot carrier performance.