Vlsi Technology, Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung S Wang

Ying T Loh

Shou-Gwo Wuu

Dun-Nian Yaung

Chenming Hu

Chen-Jong Wang

Chien-Hua Huang

Kun-Lung Chen

Chun-Yao Chen

Edward D Nowak

Ying-Tsong Loh

Yi-Ching Lin

Yi-Hen Wei

Ping Yang

Eric A Johnson

Shang-Yi Chiang

Ho-Yuan Yu

William J Boardman

Yoshiko H Strunk

Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

1T MIM memory for embedded RAM application in soc

1T MIM memory for embedded ram application in soc

The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of sensor elements configured to receive light directed towards the back surface; and an aluminum doped feature formed in the substrate and disposed horizontally between two adjacent elements of the plurality of sensor elements and vertically between the back surface and the plurality of sensor elements.

Method of making deep junction for electrical crosstalk reduction of an image sensor

Method of making a deep junction for electrical crosstalk reduction of an image sensor

An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate. A method of the present invention includes the steps of providing a semiconductor substrate, forming a gate over the substrate to define a channel, doping the substrate to form a pair of LDD regions in the substrate, doping the region to form a drain region and a source region, and doping the substrate to form a drain-side DDD region in the substrate which substantially separates the drain region from a drain-side LDD region and which substantially isolates the drain region from a bulk portion of the substrate, and to form a source-side DDD region in the substrate which substantially separates the source region from a source-side LDD region and substantially isolates the source region from a bulk portion of the substrate.

ESD and hot carrier resistant integrated circuit structure

Method of forming an ESD and hot carrier resistant integrated circuit

A bipolar transistor is fabricated in a CMOS-compatible process so as to be self-aligning, with resultant small geometry and improved high frequency performance, and to have improved hot carrier characteristics. The bipolar device has a laterally graded emitter structure that is fabricated in a 'top-down' implant process. During fabrication sidewall spacers are formed overlying the peripheral region of the laterally graded emitter. These spacers protect the underlying region against counter-doping during a subsequent intrinsic base implant, and cause the emitter and base contacts to be self-aligning. Because bipolar dimensions are thus reduced, a very narrow base width is achieved, resulting in improved device cutoff frequency. Further, a narrower emitter-base contact separation is achieved, reducing junction area and attendant junction capacitance. A base link region is formed to further improve emitter-base breakdown voltage, and to reduce extrinsic base resistance. A BiCMOS integrated circuit may be fabricated with bipolar transistors of either polarity and with MOS transistors of either polarity. BiCMOS fabrication can occur wherein substantially the same process steps are employed, or wherein specific bipolar and MOS implant steps are decoupled to optimize laterally graded emitter dopant profiles, base-link resistance, and MOS off-state leakage currents.

Method and structure for creating a self-aligned bicmos-compatible

In a method for producing an auxiliary gate lightly doped drain structure, a gate region is placed on a substrate between two source/drain regions. A first implant of atoms is made into the substrate on two sides of the gate region. Sidewalls are formed on the two sides of the gate region. Auxiliary gate regions are formed over the sidewalls. The auxiliary gate regions are separated from the gate region by the sidewalls. Dielectric regions are formed over the auxiliary gate regions. A second implant of atoms is performed into the substrate on two sides of the dielectric regions. The sidewalls and the auxiliary gate regions are composed of resistive material.

Method of fabricating auxiliary gate lightly doped drain (AGLDD)

In a method for producing a transistor with an overlapping gate region, a gate region is placed on a substrate between two source/drain regions. Spacers are placed around the gate region. The spacers are formed of dielectric material. A thin layer of polysilicon is deposited over the two source/drain regions and over electrically insulating regions adjacent to the two source/drain regions. Portions of the thin layer of polysilicon are oxidized to electrically isolate the two source/drain regions. A metal-silicide layer is formed on the portions of the thin layer of polysilicon which are not oxidized. The metal-silicide layer is connected to a metal layer. The electrical contact of the metal-silicide layer and the metal layer is over an electrically insulating layer.

Self-aligned contacts with gate overlapped lightly doped drain (goldd)

A bipolar transistor is fabricated in a CMOS-compatible process with a laterally graded emitter structure that is fabricated in a 'top-down' implant process. The laterally graded emitter decreases electric field intensities in the emitter-base junction under reverse bias, thus reducing hot carrier generation and improving emitter-base junction breakdown voltage. High current gain is further maintained by establishing sharply defined emitter-base junctions. During fabrication a blocking layer and overlying cap layer are formed in an inverted 'T' shape over a desired emitter window region. Lateral projection of the cap ledges are used to define the laterally graded emitter width, while the distance separating the cap ledges defines the width of the central emitter region. The central emitter region is implanted and driven-in to a desired depth, after which the protective cap is removed. The entire emitter window region is then implanted with a like polarity dopant of lesser dosage, which dopant is then driven-in to form laterally graded emitter junctions of a desired depth. A BiCMOS integrated circuit may be fabricated with bipolar transistors of either polarity and with MOS transistors of either polarity, using substantially the same process steps. The resultant MOS devices have lightly doped drain regions to enhance MOS hot carrier performance.

BICMOS-compatible method for creating a bipolar transistor with

A method produces a transistor with an overlapping gate. A first gate region is placed on a substrate between two source/drain regions. The first gate region includes a polysilicon region on top of a dielectric region. Gate overlap regions are placed around the polysilicon region. The gate overlap regions extend out over the two source/drain regions. The gate overlap regions are formed of a metal-silicide layer, for example Titanium-silicide. A top portion of the metal-silicide layer is oxidized to form a silicon dioxide layer on top of the metal-silicide layer. At the time of oxidation, the metal-silicide layer is also annealed to which further helps to improves the Titanium-silicide stoichiometry.

Method for producing gate overlapped lightly doped drain (GOLDD)

For a structure with an overlapping gate region, a first insulator layer is placed on a substrate. A source/drain polysilicon layer is placed on the insulator layer. The source/drain polysilicon layer is doped with atoms of a first conductivity type. A second insulator layer is placed on the source/drain polysilicon layer. A gap is etched in the second insulator layer and the source/drain polysilicon layer to expose a portion of the first insulator layer. The exposed portion of the first insulator layer and an additional amount of the first insulator layer under the second insulator is etched so as to enlarge the gap and to undercut a portion of the source/drain polysilicon layer. Two polysilicon filler regions are formed which fill a portion of the gap including the undercut area under the source/drain polysilicon layer. A gate polysilicon region is formed in the gap and extends over the source/drain polysilicon layer. The gate polysilicon region is separated from the source/drain polysilicon layer and the polysilicon filler regions by a dielectric region. Source/drain regions are formed by atoms in the source/drain polysilicon layer diffusing through the polysilicon filler regions into the substrate.

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Fremont, CA, United States of America

Chung S Wang