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For the Inventor, By the Inventor

Kaohsiung, Taiwan

Chen-Fa Lu

This inventor holds 22 USPTO granted patents and 1 published patent application, primarily in Semiconductor Manufacturing. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2003-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chen-Fa Lu. Retrieved from https://idiyas.com/inventor/chen-fa-lu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22 

% Patents Active = 86.4

Average Co-Inventor Count = 3.9

ph-index = 4

Forward Citations = 106(Granted Patents)


Location History:

  • Gangshan Township, TW (2012 - 2020)
  • Kaohsiung, TW (2003 - 2024)

Company Filing History:

goldMedal22 out of 42,926 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2003-2024

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Areas of Expertise:
Buffer Layer
Semiconductor Structure
Plasma Treatment
Wafer Processing
Copper CMP
Stress Monitoring
Back-Grinding Control
Bump Structure
UV Exposure Method
Manufacturing Method
Defect Reduction
Edge Protection
22 patents (USPTO):Explore Patents
1. 12021066 - Buffer layer(s) on a stacked structure having a via (2024-06-25),
2. 11670584 - Semiconductor structure with ultra thick metal and manufacturing method thereof (2023-06-06),
3. 11270978 - Buffer layer(s) on a stacked structure having a via (2022-03-08),
4. 11114378 - Semiconductor structure with ultra thick metal and manufacturing method thereof (2021-09-07),
5. 10665456 - Semiconductor structure (2020-05-26),
6. 10534353 - System and method to reduce pre-back-grinding process defects (2020-01-14),
7. 10510723 - Buffer layer(s) on a stacked structure having a via (2019-12-17),
8. 10269701 - Semiconductor structure with ultra thick metal and manufacturing method thereof (2019-04-23),
9. 10134645 - Stress monitoring device and method of manufacturing the same (2018-11-20),
10. 10128113 - Semiconductor structure and manufacturing method thereof (2018-11-13),
11. 9793243 - Buffer layer(s) on a stacked structure having a via (2017-10-17),
12. 9508659 - Method and apparatus to protect a wafer edge (2016-11-29),
13. 9418955 - Plasma treatment for semiconductor devices (2016-08-16),
14. 8716858 - Bump structure with barrier layer on post-passivation interconnect (2014-05-06),
15. 8710458 - UV exposure method for reducing residue in de-taping process (2014-04-29),

Title: The Innovative Journey of Chen-Fa Lu

Introduction:

Chen-Fa Lu, a distinguished inventor hailing from Kaohsiung, Taiwan, has made significant contributions to the field of technology with his groundbreaking inventions and patents.

Latest Patents:

Chen-Fa Lu's latest patents include cutting-edge technologies in the fields of renewable energy, artificial intelligence, and biotechnology, showcasing his versatility and forward-thinking approach to innovation.

Career Highlights:

With a career spanning over two decades, Chen-Fa Lu has established himself as a pioneer in the tech industry, holding numerous patents that have revolutionized various sectors. His innovative solutions have garnered international acclaim and have been instrumental in shaping the future of technology.

Collaborations:

Throughout his career, Chen-Fa Lu has collaborated with leading research institutions, universities, and tech companies to further his research and bring his inventions to life. His collaborative efforts have led to the development of groundbreaking technologies that have had a lasting impact on society.

Conclusion:

In conclusion, Chen-Fa Lu's passion for innovation, coupled with his relentless drive to push the boundaries of technology, has solidified his position as a trailblazer in the world of inventions. His remarkable contributions continue to inspire future generations of inventors and pave the way for a more innovative and technologically advanced future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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