Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Fa Lu

Chung-Shi Liu

Cheng-Yuan Tsai

Chia-Shiung Tsai

Yeur-Luen Tu

Wei-Yu Chen

Cheng-Ting Chen

Chen-Hua Douglas Yu

Chung-Long Chang

Ching-Chung Hsu

Jiech-Fun Lu

Shih-Pei Chou

Tien-Chen Hu

James Hu

Chiang-Hao Lee

Mirng-Ji Lii

Yu-Hsiang Hu

Cheng-Ta Wu

Xiaomeng Chen

Jui-Ping Chuang

Mei-Ling Chen

Chen-Peng Fan

Chin-Hsiung Ho

Shu-Ju Tsai

Liang-Kun Huang

Jin-Churng Twu

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Buffer layer(s) on a stacked structure having a via

The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.

Semiconductor structure with ultra thick metal and manufacturing method thereof

The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length extending from the dielectric layer to the ILD and a width substantially consistent along the length.

Semiconductor structure

A system for reducing processing defects during processing of a semiconductor wafer prior to back-grinding the wafer includes a table having one or more holes formed therein, wherein the table comprises at least one of a chuck table or a support table, wherein the holes are perpendicular to the surface upon which a pre-back-grinding (PBG) process occurs. The system further includes one or more sensors disposed in said holes for monitoring a parameter during the PBG process. The system further includes a computer-implemented process control tool coupled with the one or more sensors and configured to determine whether the PBG process will continue.

System and method to reduce pre-back-grinding process defects

A stress monitoring device includes an anchor structure, a freestanding structure and a Vernier structure. The anchor structure is over a substrate. The freestanding structure is over the substrate, wherein the freestanding structure is connected to the anchor structure and includes a free end suspended from the substrate. The Vernier structure is over the substrate and adjacent to the free end of the freestanding structure, wherein the Vernier structure comprises scales configured to measure a displacement of the free end of the freestanding structure.

Stress monitoring device and method of manufacturing the same

A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length running from the dielectric layer to the ILD and a width substantially consistent along the length.

Semiconductor structure and manufacturing method thereof

A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material.

Method and apparatus to protect a wafer edge

A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

Plasma treatment for semiconductor devices

A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.

Bump structure with barrier layer on post-passivation interconnect

A method of forming an integrated circuit includes providing a wafer, and a tape adhered to the wafer, wherein the tape has a main surface perpendicular to a first direction. The tape is exposed to a light to cause the tape to lose adhesion. In the step of exposing the tape, the wafer and the tape are rotated, and/or the light is tilt projected onto the tape, wherein a main projecting direction of the light and the first direction form a tilt angle greater than zero degrees and less than 90 degrees.

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Kaohsiung, Taiwan

Chen-Fa Lu