Pavia, Italy

Cesare Torti

This inventor holds 22 USPTO granted patents and 4 published patent applications and 11 EPO patents, primarily in Non-Volatile Memory. Top assignees: Stmicroelectronics S.r.l., Stmicroelectronics International N.v.. Active years: 2014-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Cesare Torti. Retrieved from https://idiyas.com/inventor/cesare-torti

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22 

% Patents Active = 86.4

 

Average Co-Inventor Count = 2.7

ph-index = 2

Forward Citations = 7(Granted Patents)


Company Filing History:


Years Active: 2014-2026

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Areas of Expertise:
Non-Volatile Memory
Phase Change Memory
Memory Device
Programming Method
Voltage Regulator
Row Decoder
Bit-Line Circuit
Reading Mode
Asymmetric Decoder
Drive Circuit
Electronic System
22 patents (USPTO):Explore Patents

Cesare Torti: Paving the Way for Non-Volatile Memory Devices

Cesare Torti is a renowned inventor in the field of non-volatile memory devices, with 17 patents to his name. His latest patents showcase his expertise in this field. One of his recent inventions is a non-volatile memory device with an asymmetric row decoder. It includes an array of memory cells coupled to word lines and a row decoder, which comprises a first and a second pull-down stage. These stages are arranged on opposite sides of the array and include, for each word line, a corresponding first and second pull-down switching circuit, respectively. Furthermore, the row decoder consists of a pull-up stage, which includes a corresponding pull-up switching circuit for each word line.

Another impressive invention of Torti is a memory device with a method for coupling a main bitline to two points of a local bitline. The memory device comprises an array of memory cells arranged in rows and columns, a plurality of local bitlines, and a plurality of main bitlines. Each main bitline can be coupled to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. Additionally, the column decoder can be electronically controlled to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines.

Torti's expertise comes from his experience in working with renowned companies like STMicroelectronics S.R.L. and STMicroelectronics International N.V. His patents have made significant contributions to the memory device technology, which has led to the development of more reliable and efficient non-volatile memory devices. Torti's coworkers like Fabio Enrico Carlo Disegni and Maurizio Francesco Perroni have also made noteworthy contributions in this field.

Cesare Torti's expertise is valuable in developing more advanced non-volatile memory devices, which are essential in modern technology. His inventions have provided a new direction in this field, inspiring other inventors and scientists to develop more efficient and reliable non-volatile memory devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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