Row decoder circuit and corresponding method of operation

Abstract

A row decoder circuit includes an input node receiving a row selection signal and an output node coupled to a memory device word line. A pull-down circuit couples the word line to ground in response to the row selection signal being asserted. A pull-up circuit couples the word line to a supply node in response to a deselection signal being de-asserted. An inverter circuit receives as input a control signal from a control node and produces the deselection signal. A current generator sources a biasing current to the control node. A further pull-down circuit couples the control node to ground in response to the row selection signal being asserted, and comprises a first cascode n-channel transistor, a cascode p-channel transistor, a second cascode n-channel transistor, and at least one selection transistor controlled by the row selection signal, all having their conductive channels arranged in series.