The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Sep. 03, 2024
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Fabio Enrico Carlo Disegni, Spino d'Adda, IT;

Marcella Carissimi, Treviolo, IT;

Cesare Torti, Pavia, IT;

Davide Manfré, Pandino, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); H03M 1/74 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 13/0004 (2013.01); H03M 1/742 (2013.01); G11C 13/0038 (2013.01);
Abstract

A circuit, a circuit for generating adaptive SET pulse currents for phase-change memory (PCM) cells is disclosed. The circuit includes a first current digital-to-analog converter (IDAC) and a second IDAC, each IDAC configured to generate a bias current with a programmable profile, the programmable profile comprising a constant current phase at a predefined set current, a first ramping-down phase from the predefined set current to a minimum cutoff current, a second ramping-down phase from the minimum cutoff current to zero, and a zero-current phase, wherein the constant current phase for each IDAC starts in response to the other IDAC starting the second ramping-down phase; and a programming circuit configured to select one of the bias currents from the first IDAC and the second IDAC and generate the adaptive SET pulse currents.


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